Move some more instruction creation methods from RegisterInfo into InstrInfo.

llvm-svn: 45484

4 files changed, 114 insertions, 120 deletions

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 7a475b0f04b..7c89ec8ced3 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -155,6 +155,101 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
   }
 }
 
+void
+AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator MI,
+                                     unsigned SrcReg, bool isKill, int FrameIdx,
+                                     const TargetRegisterClass *RC) const {
+  //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
+  //     << FrameIdx << "\n";
+  //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
+  if (RC == Alpha::F4RCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::STS))
+      .addReg(SrcReg, false, false, isKill)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else if (RC == Alpha::F8RCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::STT))
+      .addReg(SrcReg, false, false, isKill)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else if (RC == Alpha::GPRCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::STQ))
+      .addReg(SrcReg, false, false, isKill)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else
+    abort();
+}
+
+void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+                                       bool isKill,
+                                       SmallVectorImpl<MachineOperand> &Addr,
+                                       const TargetRegisterClass *RC,
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
+  unsigned Opc = 0;
+  if (RC == Alpha::F4RCRegisterClass)
+    Opc = Alpha::STS;
+  else if (RC == Alpha::F8RCRegisterClass)
+    Opc = Alpha::STT;
+  else if (RC == Alpha::GPRCRegisterClass)
+    Opc = Alpha::STQ;
+  else
+    abort();
+  MachineInstrBuilder MIB = 
+    BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+    MachineOperand &MO = Addr[i];
+    if (MO.isRegister())
+      MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+    else
+      MIB.addImm(MO.getImm());
+  }
+  NewMIs.push_back(MIB);
+}
+
+void
+AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator MI,
+                                        unsigned DestReg, int FrameIdx,
+                                        const TargetRegisterClass *RC) const {
+  //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
+  //     << FrameIdx << "\n";
+  if (RC == Alpha::F4RCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else if (RC == Alpha::F8RCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else if (RC == Alpha::GPRCRegisterClass)
+    BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+  else
+    abort();
+}
+
+void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                                        SmallVectorImpl<MachineOperand> &Addr,
+                                        const TargetRegisterClass *RC,
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
+  unsigned Opc = 0;
+  if (RC == Alpha::F4RCRegisterClass)
+    Opc = Alpha::LDS;
+  else if (RC == Alpha::F8RCRegisterClass)
+    Opc = Alpha::LDT;
+  else if (RC == Alpha::GPRCRegisterClass)
+    Opc = Alpha::LDQ;
+  else
+    abort();
+  MachineInstrBuilder MIB = 
+    BuildMI(get(Opc), DestReg);
+  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+    MachineOperand &MO = Addr[i];
+    if (MO.isRegister())
+      MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+    else
+      MIB.addImm(MO.getImm());
+  }
+  NewMIs.push_back(MIB);
+}
+
 static unsigned AlphaRevCondCode(unsigned Opcode) {
   switch (Opcode) {
   case Alpha::BEQ: return Alpha::BNE;
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.h b/llvm/lib/Target/Alpha/AlphaInstrInfo.h
index a7fd5455ac1..48e168fa9f1 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.h
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.h
@@ -47,6 +47,25 @@ public:
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,
                             const TargetRegisterClass *SrcRC) const;
+  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator MBBI,
+                                   unsigned SrcReg, bool isKill, int FrameIndex,
+                                   const TargetRegisterClass *RC) const;
+
+  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+                              SmallVectorImpl<MachineOperand> &Addr,
+                              const TargetRegisterClass *RC,
+                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                    MachineBasicBlock::iterator MBBI,
+                                    unsigned DestReg, int FrameIndex,
+                                    const TargetRegisterClass *RC) const;
+
+  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                               SmallVectorImpl<MachineOperand> &Addr,
+                               const TargetRegisterClass *RC,
+                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
   bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      std::vector<MachineOperand> &Cond) const;
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index be9cbf516f9..b5b77fe876f 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -58,101 +58,6 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
 {
 }
 
-void
-AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator MI,
-                                     unsigned SrcReg, bool isKill, int FrameIdx,
-                                     const TargetRegisterClass *RC) const {
-  //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
-  //     << FrameIdx << "\n";
-  //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
-  if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::STS))
-      .addReg(SrcReg, false, false, isKill)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::STT))
-      .addReg(SrcReg, false, false, isKill)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::STQ))
-      .addReg(SrcReg, false, false, isKill)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else
-    abort();
-}
-
-void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                       bool isKill,
-                                       SmallVectorImpl<MachineOperand> &Addr,
-                                       const TargetRegisterClass *RC,
-                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  unsigned Opc = 0;
-  if (RC == Alpha::F4RCRegisterClass)
-    Opc = Alpha::STS;
-  else if (RC == Alpha::F8RCRegisterClass)
-    Opc = Alpha::STT;
-  else if (RC == Alpha::GPRCRegisterClass)
-    Opc = Alpha::STQ;
-  else
-    abort();
-  MachineInstrBuilder MIB = 
-    BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
-  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-    MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
-      MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
-    else
-      MIB.addImm(MO.getImm());
-  }
-  NewMIs.push_back(MIB);
-}
-
-void
-AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
-                                        unsigned DestReg, int FrameIdx,
-                                        const TargetRegisterClass *RC) const {
-  //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
-  //     << FrameIdx << "\n";
-  if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else
-    abort();
-}
-
-void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                        SmallVectorImpl<MachineOperand> &Addr,
-                                        const TargetRegisterClass *RC,
-                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  unsigned Opc = 0;
-  if (RC == Alpha::F4RCRegisterClass)
-    Opc = Alpha::LDS;
-  else if (RC == Alpha::F8RCRegisterClass)
-    Opc = Alpha::LDT;
-  else if (RC == Alpha::GPRCRegisterClass)
-    Opc = Alpha::LDQ;
-  else
-    abort();
-  MachineInstrBuilder MIB = 
-    BuildMI(TII.get(Opc), DestReg);
-  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-    MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
-      MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
-    else
-      MIB.addImm(MO.getImm());
-  }
-  NewMIs.push_back(MIB);
-}
-
 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
                                                  SmallVectorImpl<unsigned> &Ops,
                                                  int FrameIndex) const {
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
index 79ecee803eb..deabc7fcd09 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -28,26 +28,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
   AlphaRegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
-  void storeRegToStackSlot(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MBBI,
-                           unsigned SrcReg, bool isKill, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
-
-  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
-                      SmallVectorImpl<MachineOperand> &Addr,
-                      const TargetRegisterClass *RC,
-                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-  void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                            MachineBasicBlock::iterator MBBI,
-                            unsigned DestReg, int FrameIndex,
-                            const TargetRegisterClass *RC) const;
-  
-  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVectorImpl<MachineOperand> &Addr,
-                       const TargetRegisterClass *RC,
-                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
   MachineInstr* foldMemoryOperand(MachineInstr* MI,
                                   SmallVectorImpl<unsigned> &Ops,
                                   int FrameIndex) const;
@@ -58,11 +38,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
     return 0;
   }
 
-  void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                    unsigned DestReg, unsigned SrcReg,
-                    const TargetRegisterClass *DestRC,
-                    const TargetRegisterClass *SrcRC) const;
-
   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                      unsigned DestReg, const MachineInstr *Orig) const;