summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Alpha/AlphaInstrInfo.h
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaInstrInfo.h')
-rw-r--r--llvm/lib/Target/Alpha/AlphaInstrInfo.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.h b/llvm/lib/Target/Alpha/AlphaInstrInfo.h
index a7fd5455ac1..48e168fa9f1 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.h
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.h
@@ -47,6 +47,25 @@ public:
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const;
OpenPOWER on IntegriCloud