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author | Chris Lattner <sabre@nondot.org> | 2006-08-17 22:00:08 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-08-17 22:00:08 +0000 |
commit | 60f1eecd3a542be630d1fcdd2c792945dfb6587d (patch) | |
tree | 4eaa3e1ef8c06f1f37a58c6acf3ea24e3784e5bc /llvm/lib/Target/Alpha | |
parent | 56588abbf87a063df92f94104f6d8e736092baab (diff) | |
download | bcm5719-llvm-60f1eecd3a542be630d1fcdd2c792945dfb6587d.tar.gz bcm5719-llvm-60f1eecd3a542be630d1fcdd2c792945dfb6587d.zip |
Constify some methods. Patch provided by Anton Vayvod, thanks!
llvm-svn: 29756
Diffstat (limited to 'llvm/lib/Target/Alpha')
-rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.td | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index 9ea4b70893e..772840a3eb6 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -180,7 +180,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const { // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { +static bool hasFP(const MachineFunction &MF) { MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.td b/llvm/lib/Target/Alpha/AlphaRegisterInfo.td index f6cea9ee4b8..9855ce27ca7 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.td +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.td @@ -124,11 +124,11 @@ def GPRC : RegisterClass<"Alpha", [i64], 64, R15, R30, R31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GPRCClass::iterator - GPRCClass::allocation_order_end(MachineFunction &MF) const { + GPRCClass::allocation_order_end(const MachineFunction &MF) const { return end()-3; } }]; @@ -142,11 +142,11 @@ def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, F31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ F4RCClass::iterator - F4RCClass::allocation_order_end(MachineFunction &MF) const { + F4RCClass::allocation_order_end(const MachineFunction &MF) const { return end()-1; } }]; @@ -160,11 +160,11 @@ def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, F31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ F8RCClass::iterator - F8RCClass::allocation_order_end(MachineFunction &MF) const { + F8RCClass::allocation_order_end(const MachineFunction &MF) const { return end()-1; } }]; |