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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2017-09-25 17:19:50 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2017-09-25 17:19:50 +0000 |
| commit | ae4de58a5b34f2a2a22d3011a2431b97b050e113 (patch) | |
| tree | 99777ffa81667691c342ac97cb214345d02754f4 /llvm/lib/Target/ARM | |
| parent | f5db0b36ff3b776a7c7119d9149c62661daa7228 (diff) | |
| download | bcm5719-llvm-ae4de58a5b34f2a2a22d3011a2431b97b050e113.tar.gz bcm5719-llvm-ae4de58a5b34f2a2a22d3011a2431b97b050e113.zip | |
ARM: Use the proper swifterror CSR list on platforms other than darwin
Noticed by inspection
llvm-svn: 314121
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCallingConv.td | 3 |
2 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index ee55cd6f9ea..18047563b74 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -94,7 +94,10 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (STI.getTargetLowering()->supportSwiftError() && F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) - return CSR_iOS_SwiftError_SaveList; + if (STI.isTargetDarwin()) + return CSR_iOS_SwiftError_SaveList; + else + return CSR_AAPCS_SwiftError_SaveList; if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS) return MF->getInfo<ARMFunctionInfo>()->isSplitCSR() @@ -122,7 +125,10 @@ ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF, if (STI.getTargetLowering()->supportSwiftError() && MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) - return CSR_iOS_SwiftError_RegMask; + if (STI.isTargetDarwin()) + return CSR_iOS_SwiftError_RegMask; + else + return CSR_AAPCS_SwiftError_RegMask; if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS) return CSR_iOS_CXX_TLS_RegMask; diff --git a/llvm/lib/Target/ARM/ARMCallingConv.td b/llvm/lib/Target/ARM/ARMCallingConv.td index bc7afdb7f1c..0404b14f0a6 100644 --- a/llvm/lib/Target/ARM/ARMCallingConv.td +++ b/llvm/lib/Target/ARM/ARMCallingConv.td @@ -247,6 +247,9 @@ def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>; def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, (sequence "D%u", 15, 8))>; +// R8 is used to pass swifterror, remove it from CSR. +def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>; + // The order of callee-saved registers needs to match the order we actually push // them in FrameLowering, because this order is what's used by // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame |
