ARM: Use the proper swifterror CSR list on platforms other than darwin

Noticed by inspection

llvm-svn: 314121

3 files changed, 53 insertions, 44 deletions

diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index ee55cd6f9ea..18047563b74 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -94,7 +94,10 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 
   if (STI.getTargetLowering()->supportSwiftError() &&
       F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
-    return CSR_iOS_SwiftError_SaveList;
+    if (STI.isTargetDarwin())
+      return CSR_iOS_SwiftError_SaveList;
+    else
+      return CSR_AAPCS_SwiftError_SaveList;
 
   if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
     return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
@@ -122,7 +125,10 @@ ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
 
   if (STI.getTargetLowering()->supportSwiftError() &&
       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
-    return CSR_iOS_SwiftError_RegMask;
+    if (STI.isTargetDarwin())
+      return CSR_iOS_SwiftError_RegMask;
+    else
+      return CSR_AAPCS_SwiftError_RegMask;
 
   if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
     return CSR_iOS_CXX_TLS_RegMask;
diff --git a/llvm/lib/Target/ARM/ARMCallingConv.td b/llvm/lib/Target/ARM/ARMCallingConv.td
index bc7afdb7f1c..0404b14f0a6 100644
--- a/llvm/lib/Target/ARM/ARMCallingConv.td
+++ b/llvm/lib/Target/ARM/ARMCallingConv.td
@@ -247,6 +247,9 @@ def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
                                      (sequence "D%u", 15, 8))>;
 
+// R8 is used to pass swifterror, remove it from CSR.
+def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
+
 // The order of callee-saved registers needs to match the order we actually push
 // them in FrameLowering, because this order is what's used by
 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll
index 8b753923ec9..da7bbdb93d0 100644
--- a/llvm/test/CodeGen/ARM/swifterror.ll
+++ b/llvm/test/CodeGen/ARM/swifterror.ll
@@ -506,48 +506,48 @@ declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_e
 ; CHECK-ARMV7:  pop     {r4, r5, r6, r7, r10, r11, pc}
 
 ; CHECK-ANDROID-LABEL: params_and_return_in_reg
-; CHECK-ANDROID:  push	{r4, r5, r6, r7, r10, r11, lr}
-; CHECK-ANDROID:  sub	sp, sp, #12
-; CHECK-ANDROID:  mov	r5, r8
-; CHECK-ANDROID:  str	r10, [sp, #4]           @ 4-byte Spill
-; CHECK-ANDROID:  mov	r6, r3
-; CHECK-ANDROID:  mov	r7, r2
-; CHECK-ANDROID:  mov	r4, r1
-; CHECK-ANDROID:  mov	r11, r0
-; CHECK-ANDROID:  mov	r0, #1
-; CHECK-ANDROID:  mov	r1, #2
-; CHECK-ANDROID:  mov	r2, #3
-; CHECK-ANDROID:  mov	r3, #4
-; CHECK-ANDROID:  mov	r10, #0
-; CHECK-ANDROID:  mov	r8, #0
-; CHECK-ANDROID:  bl	params_in_reg2
-; CHECK-ANDROID:  ldr	r10, [sp, #4]           @ 4-byte Reload
-; CHECK-ANDROID:  mov	r0, r11
-; CHECK-ANDROID:  str	r8, [sp]                @ 4-byte Spill
-; CHECK-ANDROID:  mov	r1, r4
-; CHECK-ANDROID:  mov	r2, r7
-; CHECK-ANDROID:  mov	r3, r6
-; CHECK-ANDROID:  mov	r8, r5
-; CHECK-ANDROID:  bl	params_and_return_in_reg2
-; CHECK-ANDROID:  mov	r11, r8
-; CHECK-ANDROID:  ldr	r8, [sp]                @ 4-byte Reload
-; CHECK-ANDROID:  mov	r4, r0
-; CHECK-ANDROID:  mov	r6, r1
-; CHECK-ANDROID:  mov	r7, r2
-; CHECK-ANDROID:  mov	r5, r3
-; CHECK-ANDROID:  mov	r0, #1
-; CHECK-ANDROID:  mov	r1, #2
-; CHECK-ANDROID:  mov	r2, #3
-; CHECK-ANDROID:  mov	r3, #4
-; CHECK-ANDROID:  mov	r10, #0
-; CHECK-ANDROID:  bl	params_in_reg2
-; CHECK-ANDROID:  mov	r0, r4
-; CHECK-ANDROID:  mov	r1, r6
-; CHECK-ANDROID:  mov	r2, r7
-; CHECK-ANDROID:  mov	r3, r5
-; CHECK-ANDROID:  mov	r8, r11
-; CHECK-ANDROID:  add	sp, sp, #12
-; CHECK-ANDROID:  pop	{r4, r5, r6, r7, r10, r11, pc}
+; CHECK-ANDROID:  push    {r4, r5, r6, r7, r9, r10, r11, lr}
+; CHECK-ANDROID:  sub     sp, sp, #16
+; CHECK-ANDROID:  str     r8, [sp, #4]            @ 4-byte Spill
+; CHECK-ANDROID:  mov     r11, r10
+; CHECK-ANDROID:  mov     r6, r3
+; CHECK-ANDROID:  mov     r7, r2
+; CHECK-ANDROID:  mov     r4, r1
+; CHECK-ANDROID:  mov     r5, r0
+; CHECK-ANDROID:  mov     r0, #1
+; CHECK-ANDROID:  mov     r1, #2
+; CHECK-ANDROID:  mov     r2, #3
+; CHECK-ANDROID:  mov     r3, #4
+; CHECK-ANDROID:  mov     r10, #0
+; CHECK-ANDROID:  mov     r8, #0
+; CHECK-ANDROID:  bl      params_in_reg2
+; CHECK-ANDROID:  mov     r9, r8
+; CHECK-ANDROID:  ldr     r8, [sp, #4]            @ 4-byte Reload
+; CHECK-ANDROID:  mov     r0, r5
+; CHECK-ANDROID:  mov     r1, r4
+; CHECK-ANDROID:  mov     r2, r7
+; CHECK-ANDROID:  mov     r3, r6
+; CHECK-ANDROID:  mov     r10, r11
+; CHECK-ANDROID:  bl      params_and_return_in_reg2
+; CHECK-ANDROID:  mov     r4, r0
+; CHECK-ANDROID:  mov     r5, r1
+; CHECK-ANDROID:  mov     r6, r2
+; CHECK-ANDROID:  mov     r7, r3
+; CHECK-ANDROID:  mov     r11, r8
+; CHECK-ANDROID:  mov     r0, #1
+; CHECK-ANDROID:  mov     r1, #2
+; CHECK-ANDROID:  mov     r2, #3
+; CHECK-ANDROID:  mov     r3, #4
+; CHECK-ANDROID:  mov     r10, #0
+; CHECK-ANDROID:  mov     r8, r9
+; CHECK-ANDROID:  bl      params_in_reg2
+; CHECK-ANDROID:  mov     r0, r4
+; CHECK-ANDROID:  mov     r1, r5
+; CHECK-ANDROID:  mov     r2, r6
+; CHECK-ANDROID:  mov     r3, r7
+; CHECK-ANDROID:  mov     r8, r11
+; CHECK-ANDROID:  add     sp, sp, #16
+; CHECK-ANDROID:  pop	{r4, r5, r6, r7, r9, r10, r11, pc}
 
 define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
   %error_ptr_ref = alloca swifterror %swift_error*, align 8