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authorOwen Anderson <resistor@mac.com>2011-08-11 19:00:18 +0000
committerOwen Anderson <resistor@mac.com>2011-08-11 19:00:18 +0000
commit3477f2cea5341034d154e2fd977c9ab470d609b7 (patch)
tree040509ff82a133f1ddbd80be4ac34dff7387a788 /llvm/lib/Target/ARM
parent043c820800e69427fdbd0b5c17b848cb43be6128 (diff)
downloadbcm5719-llvm-3477f2cea5341034d154e2fd977c9ab470d609b7.tar.gz
bcm5719-llvm-3477f2cea5341034d154e2fd977c9ab470d609b7.zip
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 8a85cfade1c..85e48c7165e 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -978,6 +978,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
else if (!P && writeback)
idx_mode = ARMII::IndexModePost;
+ if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE
+
if (reg) {
if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
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