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| author | Diana Picus <diana.picus@linaro.org> | 2017-02-24 13:07:25 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-02-24 13:07:25 +0000 |
| commit | 1f432f995ad444b3b362f26d204723d8e9da4635 (patch) | |
| tree | bea776e13d48d7f85194ddfa1fec2b46d88df091 /llvm/lib/Target/ARM | |
| parent | 798ad9a1e8c36492f9848e4b9a9cc013d0692c08 (diff) | |
| download | bcm5719-llvm-1f432f995ad444b3b362f26d204723d8e9da4635.tar.gz bcm5719-llvm-1f432f995ad444b3b362f26d204723d8e9da4635.zip | |
[ARM] GlobalISel: Add reg bank mappings for stores
Same as the ones for loads.
llvm-svn: 296115
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index d66bc4644c2..8a53e719c36 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -181,6 +181,7 @@ const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( case GPRRegClassID: case GPRnopcRegClassID: case tGPR_and_tcGPRRegClassID: + case tGPRRegClassID: return getRegBank(ARM::GPRRegBankID); case SPR_8RegClassID: case SPRRegClassID: @@ -224,6 +225,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; case G_LOAD: + case G_STORE: OperandsMapping = Ty.getSizeInBits() == 64 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], |
