From 1f432f995ad444b3b362f26d204723d8e9da4635 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Fri, 24 Feb 2017 13:07:25 +0000 Subject: [ARM] GlobalISel: Add reg bank mappings for stores Same as the ones for loads. llvm-svn: 296115 --- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target/ARM') diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index d66bc4644c2..8a53e719c36 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -181,6 +181,7 @@ const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( case GPRRegClassID: case GPRnopcRegClassID: case tGPR_and_tcGPRRegClassID: + case tGPRRegClassID: return getRegBank(ARM::GPRRegBankID); case SPR_8RegClassID: case SPRRegClassID: @@ -224,6 +225,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; case G_LOAD: + case G_STORE: OperandsMapping = Ty.getSizeInBits() == 64 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], -- cgit v1.2.3