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| author | Tim Northover <tnorthover@apple.com> | 2016-03-17 20:10:28 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-03-17 20:10:28 +0000 |
| commit | 498c56c240ba8e0a0de97e7137ec8c791e79a64d (patch) | |
| tree | 06b910592e26c0555bee944ca3fd199cb39f4955 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 4084504caac224362f918a8b74a747dd8c1fdd0f (diff) | |
| download | bcm5719-llvm-498c56c240ba8e0a0de97e7137ec8c791e79a64d.tar.gz bcm5719-llvm-498c56c240ba8e0a0de97e7137ec8c791e79a64d.zip | |
ARM: stop asserting on weird <3 x Ty> vectors in ISelLowering.
llvm-svn: 263741
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index bb470c2c241..9cd880d719d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10124,7 +10124,8 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || + Op.getOpcode() != ISD::FMUL) return SDValue(); SDValue ConstVec = Op->getOperand(1); @@ -10181,7 +10182,7 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, SDValue Op = N->getOperand(0); unsigned OpOpcode = Op.getNode()->getOpcode(); - if (!N->getValueType(0).isVector() || + if (!N->getValueType(0).isVector() || !N->getValueType(0).isSimple() || (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) return SDValue(); |
