ARM: stop asserting on weird <3 x Ty> vectors in ISelLowering.

llvm-svn: 263741

3 files changed, 19 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index bb470c2c241..9cd880d719d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10124,7 +10124,8 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
     return SDValue();
 
   SDValue Op = N->getOperand(0);
-  if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
+  if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
+      Op.getOpcode() != ISD::FMUL)
     return SDValue();
 
   SDValue ConstVec = Op->getOperand(1);
@@ -10181,7 +10182,7 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
 
   SDValue Op = N->getOperand(0);
   unsigned OpOpcode = Op.getNode()->getOpcode();
-  if (!N->getValueType(0).isVector() ||
+  if (!N->getValueType(0).isVector() || !N->getValueType(0).isSimple() ||
       (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
     return SDValue();
 
diff --git a/llvm/test/CodeGen/ARM/vcvt_combine.ll b/llvm/test/CodeGen/ARM/vcvt_combine.ll
index 9a8f084d230..11bed5a1a47 100644
--- a/llvm/test/CodeGen/ARM/vcvt_combine.ll
+++ b/llvm/test/CodeGen/ARM/vcvt_combine.ll
@@ -62,3 +62,11 @@ define <4 x i32> @t5(<4 x float> %in) {
   %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
   ret <4 x i32> %vcvt.i
 }
+
+; CHECK-LABEL: test_illegal_fp_to_int:
+; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2
+define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
+  %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
+  %val = fptosi <3 x float> %scale to <3 x i32>
+  ret <3 x i32> %val
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/ARM/vdiv_combine.ll b/llvm/test/CodeGen/ARM/vdiv_combine.ll
index 8511dbcb687..4a6c36b4277 100644
--- a/llvm/test/CodeGen/ARM/vdiv_combine.ll
+++ b/llvm/test/CodeGen/ARM/vdiv_combine.ll
@@ -153,3 +153,11 @@ define <4 x float> @test8(<4 x i32> %in) {
   %div.i = fdiv <4 x float> %vcvt.i, <float 2.0, float 2.0, float 2.0, float undef>
   ret <4 x float> %div.i
 }
+
+; CHECK-LABEL: test_illegal_int_to_fp:
+; CHECK: vcvt.f32.s32
+define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {
+  %conv = sitofp <3 x i32> %in to <3 x float>
+  %res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>
+  ret <3 x float> %res
+}
\ No newline at end of file