diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 9012b3110b3..ac569d967c1 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -589,9 +589,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, .addImm(i * 4) // offset .addMemOperand(MMO); BuildMI(*MBB, MI, DL, - TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg) + TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) .addReg(TmpReg, RegState::Kill) - .addImm(0) .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); } } diff --git a/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll b/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll index 0731a4e1ec0..5171406469a 100644 --- a/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll +++ b/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll @@ -5,7 +5,7 @@ ; Make sure we are handling hazards correctly. ; CHECK: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12 ; CHECK-NEXT: s_waitcnt vmcnt(0) -; CHECK-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]] +; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]] ; CHECK-NEXT: s_nop 4 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0 ; CHECK: s_endpgm |
