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authorAmara Emerson <aemerson@apple.com>2018-06-01 13:20:32 +0000
committerAmara Emerson <aemerson@apple.com>2018-06-01 13:20:32 +0000
commit5a3bb68e12e4315b9efd662e499cde7e15cdec04 (patch)
treee5c677243bcd05556033c384ed91fd45d69926b2 /llvm/lib/Target/AArch64
parented6bc3422636dc8d4de58d18f319ae0b56827de9 (diff)
downloadbcm5719-llvm-5a3bb68e12e4315b9efd662e499cde7e15cdec04.tar.gz
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[AArch64][GlobalISel] Zero-extend s1 values when returning.
Before we were relying on the any extend of the s1 to s32, but for AAPCS we need to zero-extend it to at least s8. Fixes PR36719 Differential Revision: https://reviews.llvm.org/D47425 llvm-svn: 333747
Diffstat (limited to 'llvm/lib/Target/AArch64')
-rw-r--r--llvm/lib/Target/AArch64/AArch64CallLowering.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
index 1914f56a562..e4dc10cbf7b 100644
--- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -229,9 +229,14 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
bool Success = true;
if (VReg) {
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ // We zero-extend i1s to i8.
+ if (MRI.getType(VReg).getSizeInBits() == 1)
+ VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg();
+
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
- MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();
ArgInfo OrigArg{VReg, Val->getType()};
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