diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 11 |
3 files changed, 18 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index b5cc7f7727f..87086af121b 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -726,17 +726,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { WideTy != LLT::scalar(8)) return UnableToLegalize; - const auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); - switch (TLI.getBooleanContents(false, false)) { - case TargetLoweringBase::ZeroOrNegativeOneBooleanContent: - widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_SEXT); - break; - case TargetLoweringBase::ZeroOrOneBooleanContent: - widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT); - break; - default: - widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT); - } + widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT); MIRBuilder.recordInsertion(&MI); return Legalized; } diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp index 1914f56a562..e4dc10cbf7b 100644 --- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp @@ -229,9 +229,14 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg"); bool Success = true; if (VReg) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + + // We zero-extend i1s to i8. + if (MRI.getType(VReg).getSizeInBits() == 1) + VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg(); + const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv()); - MachineRegisterInfo &MRI = MF.getRegInfo(); auto &DL = F.getParent()->getDataLayout(); ArgInfo OrigArg{VReg, Val->getType()}; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 013d0879c3a..7644322f9d4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1859,3 +1859,14 @@ define void @test_nested_aggregate_const(%agg.nested *%ptr) { store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, %agg.nested *%ptr ret void } + +define i1 @return_i1_zext() { +; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend. +; CHECK-LABEL: name: return_i1_zext +; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true +; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1) +; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8) +; CHECK: $w0 = COPY [[ANYEXT]](s32) +; CHECK: RET_ReallyLR implicit $w0 + ret i1 true +} |
