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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 16:58:31 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 16:58:31 +0000 |
| commit | 61a7928dde74b36b1c3a75eb17c178e70182e045 (patch) | |
| tree | 9a4932715dbc3c56cdcba102ac017451dba88bce /llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | |
| parent | 46c05fc861c49b82e049aefd9799bc39edb2b768 (diff) | |
| download | bcm5719-llvm-61a7928dde74b36b1c3a75eb17c178e70182e045.tar.gz bcm5719-llvm-61a7928dde74b36b1c3a75eb17c178e70182e045.zip | |
[AArch64][GlobalISel] Select GPR G_AND.
llvm-svn: 277002
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 26b574af464..db8bfc9aac9 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRWrr; + case TargetOpcode::G_AND: + return AArch64::ANDWrr; case TargetOpcode::G_ADD: return AArch64::ADDWrr; default: @@ -61,6 +63,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRXrr; + case TargetOpcode::G_AND: + return AArch64::ANDXrr; case TargetOpcode::G_ADD: return AArch64::ADDXrr; default: @@ -105,6 +109,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { switch (I.getOpcode()) { case TargetOpcode::G_OR: + case TargetOpcode::G_AND: case TargetOpcode::G_ADD: { DEBUG(dbgs() << "AArch64: Selecting: binop\n"); |

