From 61a7928dde74b36b1c3a75eb17c178e70182e045 Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Thu, 28 Jul 2016 16:58:31 +0000 Subject: [AArch64][GlobalISel] Select GPR G_AND. llvm-svn: 277002 --- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp') diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 26b574af464..db8bfc9aac9 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRWrr; + case TargetOpcode::G_AND: + return AArch64::ANDWrr; case TargetOpcode::G_ADD: return AArch64::ADDWrr; default: @@ -61,6 +63,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, switch (GenericOpc) { case TargetOpcode::G_OR: return AArch64::ORRXrr; + case TargetOpcode::G_AND: + return AArch64::ANDXrr; case TargetOpcode::G_ADD: return AArch64::ADDXrr; default: @@ -105,6 +109,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { switch (I.getOpcode()) { case TargetOpcode::G_OR: + case TargetOpcode::G_AND: case TargetOpcode::G_ADD: { DEBUG(dbgs() << "AArch64: Selecting: binop\n"); -- cgit v1.2.3