From b52e0366008436f6f994ce94cb6ad0f51d65ba8a Mon Sep 17 00:00:00 2001
From: Francis Visoiu Mistrih <fvisoiumistrih@apple.com>
Date: Wed, 17 May 2017 01:07:53 +0000
Subject: BitVector: add iterators for set bits

Differential revision: https://reviews.llvm.org/D32060

llvm-svn: 303227
---
 llvm/lib/CodeGen/TargetRegisterInfo.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'llvm/lib/CodeGen/TargetRegisterInfo.cpp')

diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index f6e4c17d514..41ec082a24c 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -50,8 +50,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
     ArrayRef<MCPhysReg> Exceptions) const {
   // Check that all super registers of reserved regs are reserved as well.
   BitVector Checked(getNumRegs());
-  for (int Reg = RegisterSet.find_first(); Reg>=0;
-       Reg = RegisterSet.find_next(Reg)) {
+  for (unsigned Reg : RegisterSet.set_bits()) {
     if (Checked[Reg])
       continue;
     for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
-- 
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