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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-03-17 17:45:36 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-03-17 17:45:36 +0000
commit5a68d401c752dd2835d483faa5029958c0599eb6 (patch)
treeeaae1f6c279de0095bb04558509b169916797301 /llvm/lib/CodeGen/SelectionDAG
parent25bd713d33c6d0fa7b1e9248ed31dfb0dbdd5845 (diff)
downloadbcm5719-llvm-5a68d401c752dd2835d483faa5029958c0599eb6.tar.gz
bcm5719-llvm-5a68d401c752dd2835d483faa5029958c0599eb6.zip
[SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABS
llvm-svn: 298108
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d860449de75..90987d38744 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2730,6 +2730,26 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
KnownOne = KnownOne2.byteSwap();
break;
}
+ case ISD::ABS: {
+ computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
+ Depth + 1);
+
+ // If the source's MSB is zero then we know the rest of the bits already.
+ if (KnownZero2[BitWidth - 1]) {
+ KnownZero = KnownZero2;
+ KnownOne = KnownOne2;
+ break;
+ }
+
+ // We only know that the absolute values's MSB will be zero iff there is
+ // a set bit that isn't the sign bit (otherwise it could be INT_MIN).
+ KnownOne2.clearBit(BitWidth - 1);
+ if (KnownOne2.getBoolValue()) {
+ KnownZero = APInt::getSignBit(BitWidth);
+ break;
+ }
+ break;
+ }
case ISD::UMIN: {
computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
Depth + 1);
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