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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-17 17:45:36 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-17 17:45:36 +0000 |
| commit | 5a68d401c752dd2835d483faa5029958c0599eb6 (patch) | |
| tree | eaae1f6c279de0095bb04558509b169916797301 | |
| parent | 25bd713d33c6d0fa7b1e9248ed31dfb0dbdd5845 (diff) | |
| download | bcm5719-llvm-5a68d401c752dd2835d483faa5029958c0599eb6.tar.gz bcm5719-llvm-5a68d401c752dd2835d483faa5029958c0599eb6.zip | |
[SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABS
llvm-svn: 298108
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/known-bits-vector.ll | 12 |
2 files changed, 22 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index d860449de75..90987d38744 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2730,6 +2730,26 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, KnownOne = KnownOne2.byteSwap(); break; } + case ISD::ABS: { + computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts, + Depth + 1); + + // If the source's MSB is zero then we know the rest of the bits already. + if (KnownZero2[BitWidth - 1]) { + KnownZero = KnownZero2; + KnownOne = KnownOne2; + break; + } + + // We only know that the absolute values's MSB will be zero iff there is + // a set bit that isn't the sign bit (otherwise it could be INT_MIN). + KnownOne2.clearBit(BitWidth - 1); + if (KnownOne2.getBoolValue()) { + KnownZero = APInt::getSignBit(BitWidth); + break; + } + break; + } case ISD::UMIN: { computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, Depth + 1); diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll index 7c4afc6f2e4..d10b865e438 100644 --- a/llvm/test/CodeGen/X86/known-bits-vector.ll +++ b/llvm/test/CodeGen/X86/known-bits-vector.ll @@ -590,11 +590,7 @@ define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) { ; X32-NEXT: vpor {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2] ; X32-NEXT: vpabsd %xmm0, %xmm0 -; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] -; X32-NEXT: vpsrld $16, %xmm0, %xmm0 -; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] -; X32-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0 -; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0 +; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: knownbits_or_abs_uitofp: @@ -602,11 +598,7 @@ define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) { ; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2] ; X64-NEXT: vpabsd %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] -; X64-NEXT: vpsrld $16, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] -; X64-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 -; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0 +; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X64-NEXT: retq %1 = or <4 x i32> %a0, <i32 1, i32 0, i32 3, i32 0> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> |
