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| author | Sam Parker <sam.parker@arm.com> | 2018-01-18 09:22:24 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2018-01-18 09:22:24 +0000 |
| commit | 1f8c035d6bbafee49b364cedea9034b2a7e39fff (patch) | |
| tree | 8a1d5f86401e391fd23beee1cd097fa46ee18885 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 0e9a8a5f6f91f843c612af23005980a36d3766fe (diff) | |
| download | bcm5719-llvm-1f8c035d6bbafee49b364cedea9034b2a7e39fff.tar.gz bcm5719-llvm-1f8c035d6bbafee49b364cedea9034b2a7e39fff.zip | |
[SelectionDAG] Convert assert to condtion
Follow-up to r322120 which can cause assertions for AArch64 because
v1f64 and v1i64 are legal types.
Differential Revision: https://reviews.llvm.org/D42097
llvm-svn: 322823
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 69d9fe979db..ce944115c6e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -171,10 +171,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { SDValue Op = N->getOperand(0); if (Op.getValueType().isVector() - && Op.getValueType().getVectorNumElements() == 1) { - assert(!isSimpleLegalType(Op.getValueType())); + && Op.getValueType().getVectorNumElements() == 1 + && !isSimpleLegalType(Op.getValueType())) Op = GetScalarizedVector(Op); - } EVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BITCAST, SDLoc(N), NewVT, Op); |
