From 1f8c035d6bbafee49b364cedea9034b2a7e39fff Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Thu, 18 Jan 2018 09:22:24 +0000 Subject: [SelectionDAG] Convert assert to condtion Follow-up to r322120 which can cause assertions for AArch64 because v1f64 and v1i64 are legal types. Differential Revision: https://reviews.llvm.org/D42097 llvm-svn: 322823 --- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'llvm/lib/CodeGen/SelectionDAG') diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 69d9fe979db..ce944115c6e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -171,10 +171,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { SDValue Op = N->getOperand(0); if (Op.getValueType().isVector() - && Op.getValueType().getVectorNumElements() == 1) { - assert(!isSimpleLegalType(Op.getValueType())); + && Op.getValueType().getVectorNumElements() == 1 + && !isSimpleLegalType(Op.getValueType())) Op = GetScalarizedVector(Op); - } EVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BITCAST, SDLoc(N), NewVT, Op); -- cgit v1.2.3