vhdl2vl - vhdl2vl

	Commit message (Collapse)	Author	Age	Files	Lines
*	Moved unsupported commented things to todo.vhd	Rodrigo Alejandro Melo	2017-11-27	1	-3/+0
\|
*	Correct selection of -: vs. +:	Larry Doolittle	2017-11-25	1	-21/+21
\| \| \| \| \|	Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd
*	Turn off debug prints and fix warnings	Larry Doolittle	2017-11-23	1	-6/+15
\|
*	First stupid attempt to finish part select	Larry Doolittle	2017-11-23	1	-22/+22
\| \| \| \| \|	No attempt to figure out -: vs. +: Already yields much better results on test files
*	Removed unuseful parentheses	Rodrigo Alejandro Melo	2017-11-17	1	-9/+9
\|
*	Modified to use ',' to separate sensitivity list in verilog 2001	Rodrigo Alejandro Melo	2017-02-17	1	-7/+7
\| \| \| \|	Changes applied to translated_examples.
*	Changed translated_examples due that Verilog 2001 is now the default	Rodrigo Alejandro Melo	2017-02-17	1	-81/+27
\|
*	Added command line option --quiet	Rodrigo Alejandro Melo	2017-02-17	1	-21/+0
\| \| \| \| \|	Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples.
*	Space deleted in the <size>'<radix><number> notation	Rodrigo Alejandro Melo	2017-02-09	1	-59/+59
\| \| \| \| \| \| \|	It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified.
*	vhd2vl-2.5	Larry Doolittle	2015-09-20	1	-2/+2
\|
*	vhd2vl-2.4	Larry Doolittle	2015-09-20	1	-8/+11
\|
*	vhd2vl-2.3	Larry Doolittle	2015-09-20	1	-2/+2
\|
*	vhd2vl-2.2	Larry Doolittle	2015-09-20	1	-0/+501