Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Examples were corrected according to GHDL complains | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
* | Squelch some trailing whitespace | Larry Doolittle | 2017-11-12 | 1 | -2/+2 |
* | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 1 | -0/+36 |