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authorRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-16 10:42:10 -0300
committerRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-16 10:42:10 -0300
commit194af658cd6a9021999d5e416a7a0a04d8dc4fa8 (patch)
treeb756a4dffb1371ea0110f944eaab1ffc0680949b /examples/mem.vhd
parent1afbdf0b2553d000b265d3cf76fce4d069cfa7ce (diff)
downloadvhdl2vl-194af658cd6a9021999d5e416a7a0a04d8dc4fa8.tar.gz
vhdl2vl-194af658cd6a9021999d5e416a7a0a04d8dc4fa8.zip
Examples were corrected according to GHDL complains
Diffstat (limited to 'examples/mem.vhd')
-rw-r--r--examples/mem.vhd4
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/mem.vhd b/examples/mem.vhd
index 7b96b65..408051f 100644
--- a/examples/mem.vhd
+++ b/examples/mem.vhd
@@ -23,13 +23,13 @@ architecture rtl of mem is
signal mem : mem_Type;
signal al : unsigned(addr_width-1 downto 0) := X"00";
begin
- dout <= mem(al);
+ dout <= mem(to_integer(al));
process (clk) is
begin
if rising_edge(clk) then
al <= addr;
if en = '1' then
- mem(addr) <= din;
+ mem(to_integer(addr)) <= din;
end if;
end if;
end process;
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