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The idea is to put there things that don't work or that could be improved.
Is ignored in the main Makefile when target 'translate' is used.
The target 'todo' was added to the main Makefile.
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Requires iverilog to operate.
Scans resulting files in translated_examples directory.
This patch includes some simple fixes to reduce the number of errors reported,
but there are more that need further investigation.
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Allow people without GHDL installed to make the diff target
Make it clear when the diff target succeeds
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Used to avoid header on the generated verilog file. Is a problem for regression tests.
Header was removed from translated_examples.
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* -d is now --debug
* -g1995 and -g2001 are now --std 1995|2001
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Some examples were corrected according GHDL complains.
Corresponding traslated_examples were modified.
Use of synopsys libraries was removed.
Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned').
The problem was comented.
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Also support was added for real numbers especially thinking in generics.
Files called scientific.vhd and scientific.v were added for test.
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It seems to be the more common approach and the VHDL notation BASE#NUMBER#
is translated without spaces. On the other hand, the space gives an error
with Yosys synthesizer.
Files on translated_examples were modified.
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