New make target: verilogcheck

Requires iverilog to operate.
Scans resulting files in translated_examples directory.
This patch includes some simple fixes to reduce the number of errors reported,
but there are more that need further investigation.

1 files changed, 4 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 7d841be..0bcd635 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,7 @@
 #!/usr/bin/make
 # by RAM 2017
 
+VERILOG = iverilog -Wall -y . -t null
 EXAMPLES = $(wildcard examples/*.vhd)
 VHDLS    = $(notdir $(EXAMPLES))
 
@@ -22,6 +23,9 @@ diff: translate
 	diff -u translated_examples temp/verilog
 	@echo "PASS"
 
+verilogcheck:
+	@cd translated_examples; for f in *.v; do $(VERILOG) $$f; done
+
 clean:
 	make -C src clean
 	@make -C examples clean