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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-16 23:54:22 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-16 23:54:22 -0300 |
| commit | a19f0441854a5602dd8865ea2eed341a5a5056de (patch) | |
| tree | 9c313415355993ec8d433c9e115119d180210300 /Makefile | |
| parent | 286f3665632a2fae3c84179cca173cfbda23b390 (diff) | |
| download | vhdl2vl-a19f0441854a5602dd8865ea2eed341a5a5056de.tar.gz vhdl2vl-a19f0441854a5602dd8865ea2eed341a5a5056de.zip | |
New command line parsing using getopt
* -d is now --debug
* -g1995 and -g2001 are now --std 1995|2001
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -11,8 +11,8 @@ src/vhd2vl: translate: src/vhd2vl @mkdir -p temp/verilog - #@make -C examples - @$(foreach VHDL,$(VHDLS),cd examples; echo "Translating: $(VHDL)";../src/vhd2vl $(VHDL) ../temp/verilog/$(basename $(VHDL)).v) + @make -C examples + @cd examples; $(foreach VHDL,$(VHDLS), echo "Translating: $(VHDL)";../src/vhd2vl $(VHDL) ../temp/verilog/$(basename $(VHDL)).v;) diff: translate @diff -u translated_examples temp/verilog |
