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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-23 18:34:08 -0800 |
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committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-23 18:34:08 -0800 |
commit | a043b124b5390380638eeec56fb143d2670af85c (patch) | |
tree | 5e47a230482db068dc3ce89716b6d6f2f04d6b82 /translated_examples/partselect.v | |
parent | d65dfa59badc67797353ff65df9ad6e73af878e9 (diff) | |
download | vhdl2vl-a043b124b5390380638eeec56fb143d2670af85c.tar.gz vhdl2vl-a043b124b5390380638eeec56fb143d2670af85c.zip |
First stupid attempt to finish part select
No attempt to figure out -: vs. +:
Already yields much better results on test files
Diffstat (limited to 'translated_examples/partselect.v')
-rw-r--r-- | translated_examples/partselect.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/translated_examples/partselect.v b/translated_examples/partselect.v index 9eba2a8..2197b0b 100644 --- a/translated_examples/partselect.v +++ b/translated_examples/partselect.v @@ -13,14 +13,15 @@ wire [31:0] i = 8; always @(posedge clk_i) begin : P1 reg [31:0] big_var; - reg [31:0] j = 8; + reg [31:0] j; + // XXX not ready for :=8; big_sig[31:24] <= big_sig[7:0]; big_var[31:24] = big_var[7:0]; lit_sig[24:31] <= lit_sig[0:7]; // - big_sig[i * 3 + 8:i * 3] <= big_sig[i - 1:0]; - big_var[j * 3 + 8:j * 3] = big_var[j * 0 + 8:j * 0]; + big_sig[i * 3 + 8+:8 + 1] <= big_sig[8:0]; + big_var[j * 3 + 8+:8 + 1] = big_var[j * 0 + 8+:8 + 1]; end |