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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-27 15:02:39 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-27 15:02:39 -0300 |
| commit | 6683eeba0e6956dc6bcb4ff967791cd125584dbc (patch) | |
| tree | fb5e38be7b9689aa81de48f7e85c317f2655210c /translated_examples/forloop.v | |
| parent | b544184b93e5fdacadab0c69a0cbfabe6fd22192 (diff) | |
| download | vhdl2vl-6683eeba0e6956dc6bcb4ff967791cd125584dbc.tar.gz vhdl2vl-6683eeba0e6956dc6bcb4ff967791cd125584dbc.zip | |
Moved unsupported commented things to todo.vhd
Diffstat (limited to 'translated_examples/forloop.v')
| -rw-r--r-- | translated_examples/forloop.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/translated_examples/forloop.v b/translated_examples/forloop.v index 88ee5f7..c54d382 100644 --- a/translated_examples/forloop.v +++ b/translated_examples/forloop.v @@ -13,7 +13,6 @@ reg [6:0] egg_timer; always @(posedge reset, posedge sysclk) begin : P1 reg [31:0] timer_var; - // XXX unhandled := 0; reg [31:0] a, i, j, k; reg [31:0] zz5; reg [511:0] zz; |
