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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-17 11:33:30 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-17 11:33:30 -0300 |
| commit | b9b93adac2d304792b33455542a84d2f310a82ef (patch) | |
| tree | 2c45383c79d0bb0754584bb972576cc20f26aa2a /translated_examples/dsp.v | |
| parent | 48dc1011e34dfdcf11f9c4b3e68145a83e53db68 (diff) | |
| download | vhdl2vl-b9b93adac2d304792b33455542a84d2f310a82ef.tar.gz vhdl2vl-b9b93adac2d304792b33455542a84d2f310a82ef.zip | |
Removed unuseful parentheses
Diffstat (limited to 'translated_examples/dsp.v')
| -rw-r--r-- | translated_examples/dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v index 23ac529..52474d3 100644 --- a/translated_examples/dsp.v +++ b/translated_examples/dsp.v @@ -27,7 +27,7 @@ parameter [31:0] bus_width=24; wire foo; always @(clk) begin - dout <= ((1)); + dout <= 1; end |
