diff options
-rw-r--r-- | GPLv2.txt | 339 | ||||
-rw-r--r-- | README.txt | 81 | ||||
-rw-r--r-- | changes | 84 | ||||
-rw-r--r-- | examples/based.vhd | 15 | ||||
-rw-r--r-- | examples/bigfile.vhd | 465 | ||||
-rw-r--r-- | examples/clk.vhd | 36 | ||||
-rw-r--r-- | examples/counters.vhd | 348 | ||||
-rw-r--r-- | examples/expr.vhd | 40 | ||||
-rw-r--r-- | examples/for.vhd | 38 | ||||
-rw-r--r-- | examples/generate.vhd | 50 | ||||
-rw-r--r-- | examples/generic.vhd | 32 | ||||
-rw-r--r-- | examples/genericmap.vhd | 79 | ||||
-rw-r--r-- | examples/ifchain.vhd | 20 | ||||
-rw-r--r-- | examples/test.vhd | 191 | ||||
-rw-r--r-- | src/def.h | 78 | ||||
-rw-r--r-- | src/makefile | 11 | ||||
-rw-r--r-- | src/vhd2vl.l | 170 | ||||
-rw-r--r-- | src/vhd2vl.y | 2145 | ||||
-rw-r--r-- | translated_examples/based.v | 39 | ||||
-rw-r--r-- | translated_examples/bigfile.v | 501 | ||||
-rw-r--r-- | translated_examples/clk.v | 72 | ||||
-rw-r--r-- | translated_examples/counters.v | 449 | ||||
-rw-r--r-- | translated_examples/expr.v | 56 | ||||
-rw-r--r-- | translated_examples/for.v | 61 | ||||
-rw-r--r-- | translated_examples/generate.v | 66 | ||||
-rw-r--r-- | translated_examples/generic.v | 70 | ||||
-rw-r--r-- | translated_examples/genericmap.v | 128 | ||||
-rw-r--r-- | translated_examples/ifchain.v | 43 | ||||
-rw-r--r-- | translated_examples/test.v | 242 |
29 files changed, 5949 insertions, 0 deletions
diff --git a/GPLv2.txt b/GPLv2.txt new file mode 100644 index 0000000..d511905 --- /dev/null +++ b/GPLv2.txt @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/README.txt b/README.txt new file mode 100644 index 0000000..836b0cb --- /dev/null +++ b/README.txt @@ -0,0 +1,81 @@ +VHD2VL v2.2 README.txt + +Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001. +It does not support the full VHDL grammar - most of the testbench +related features have been left out. See the examples and +translated_examples directories for examples of what vhd2vl can do. + +Vhd2vl does a pretty good job of translating, but you should ALWAYS +test the generated Verilog, ideally by using a formal verification +tool to compare it to the original VHDL! + +The home page for (at least for this version of) vhd2vl is + http://doolittle.icarus.com/~larry/vhd2vl/ + +1.0 HOW TO BUILD AND INSTALL vhd2vl: + +To build, just type 'make' in the src directory. + +This version of vhd2vl has been tested with GNU Bison 2.3, and +GNU Flex version 2.5.35. No problems have been reported with other +fairly recent versions. + +To install, copy the resulting src/vhd2vl file to someplace in +your $PATH, like $HOME/bin or /usr/local/bin. + + +2.0 HOW TO USE vhd2vl: + + vhd2vl VHDL_file.vhd > translated_file.v +or + vhd2vl VHDL_file.vhd translated_file.v +The two are equivalent when everything works. The latter has some +advantages when handling errors within a Makefile. + + +3.0 TROUBLESHOOTING: + +If vhd2vl complains about a syntax error, this is usually due to a +VHDL construct that vhd2vl cannot translate. Try commenting out the +offending line, and running vhd2vl again. You can then edit the +Verilog output file and manually translate the offending line of VHDL. + +Comments in the middle of statements sometimes confuse vhd2vl. This +is a "feature" of the logic that copies comments from VHDL to Verilog. +If vhd2vl complains about a syntax error caused by a comment, just +move that comment out of the middle of the statement and try again. + +The grammar has rules that recognize common ways of writing clocked +processes. Your code might contain clocked processes that do not match +any of the templates in the grammar. This usually causes VHD2VL to +complain about a clock'event expression in a process. If this +happens, a minor rewrite of that process will let you work around the +problem. + +If you need to look at the VHDL grammar, make puts a copy of it in +vhd2vl.output. If you need to change the grammar, then running vhd2vl +with the '-d' option will cause vhd2vl to trace how it is parsing the +input file. See the bison documentation for more details. + + +4.0 MISSING FEATURES AND KNOWN INCORRECT OUTPUT: + +String types: awkward, because Verilog strings need predefined length + +Attribute: easy to parse, but I'm not sure what Verilog construct + to turn it into. It smells like a parameter, not an (* attribute *). + +Multiple actions in one process, as used in DDR logic? + +Exit statement incompletely converted to disable statement + (see examples/bigfile.vhd) + +Part select expression zz(31+k downto k) should convert to zz[31+k+:32] + (see examples/for.vhd) + +variables not handled right, show up as declarations within always blocks + (see examples/for.vhd) + +Conversion functions (resize and to_unsigned) are parsed, but their + semantics are ignored: resize(foo,n) and to_unsigned(foo,n) are treated + as equivalent to (foo). @@ -0,0 +1,84 @@ +Changes 1.2 to 2.2 (Larry Doolittle, February 2009) + +Merge extensive changes from Mark Gonzales' version 2.0. Thanks, Mark! + +Grammar: + * add XNOR + * add hex strings (X"f0f0") + * remove UNIT reserved words, and actually emit timescale directive + * case statements without "when others" + * add a few more "rem"s to the grammar + * add resize to the CONVFUNC_2 list + * handle one-bit enumeration bit range correctly (no more [0]) + * some gratuitous changes in output whitespace + +Coding: + * clean up GENERIC pattern + * debug and clean up slist routines and their usage + * wrap malloc with xmalloc to exit if out of memory + * update Free Software Foundation address + + +Changes 2.0 to 2.1 (Steve Haynal, unreleased?) + +Presumably useful to Steve, but everything is too strange or scary +for me (Larry Doolittle) to understand and incorporate. Sorry, Steve, +maybe I'll get something from your work on my next iteration. People +interested in the following features (incomplete list) should contact +the developers directly: + * lower-cased identifiers in translated Verilog + * parses VHDL packages + * parses many VHDL functions and macros + * floating-point "after" construct parsed but ignored + + +Changes 1.0 to 2.0 (Mark Gonzales, June 2006) + +Grammar: + * FOR LOOP + * FOR GENERATE and IF GENERATE + * natural, integer, time types + * based numbers (16#55aa#) + * expressions can now include VHDL type conversion functions, mod operator, numbers + * now can tolerate comments in the middle of expressions + * expressions can now be used in subscripts and vector range definitions + * width on (others => 'x') can now be an expression + * uses always @(*) when creating some combinational always blocks + * variable initialization support + * constant can be initialized by an expression + * GENERIC definitions for entity are now translated into Verilog + parameter definitions, and GENERIC MAPs on instances are translated + into Verilog in-line explicit parameter definitions. + * allow entity declarations and architectures in separate files + +Operation: + * new -d option for trace parse - to debug grammar errors + +Coding: + * introduce slist data structure to build resulting Verilog + + +Changes 1.0 to 1.2 (Larry Doolittle, May 2005) + +Grammar: + * allow NATURAL as an expression terminal symbol + * allow (name'event and exprc) as process sensitivity + * allow IS syntactic sugar in COMPONENT declaration + * add a bunch of "rem"s to the grammar + * handle inout better + * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector" + +Operation: + * more complete handling of argc/argv + * if error happened, return 1 from main and remove incorrect/incomplete output files + * avoid insinuating that output Verilog is covered by GPL + +Coding: + * increase gcc warning level + * add required #includes + * remove spurious commas in bison token lists + * drop worthless malloc() casts; see C-faq/q7.7 + * prototype yylex and yyerror + * add braces around confusing if/else chain + +Original 1.0 (Vincenzo Liguori, February 2001) diff --git a/examples/based.vhd b/examples/based.vhd new file mode 100644 index 0000000..d9b5a29 --- /dev/null +++ b/examples/based.vhd @@ -0,0 +1,15 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; + +entity based is port( sysclk : in std_logic); +end based; +architecture rtl of based is + signal foo,foo2,foo8,foo10,foo11,foo16 : integer; +begin + foo <= 123; + foo2 <= 2#00101101110111#; + foo8 <= 8#0177362#; + foo10<= 10#01234#; + foo11<= 11#01234#; + foo16<= 16#12af#; +end rtl; diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd new file mode 100644 index 0000000..9d76855 --- /dev/null +++ b/examples/bigfile.vhd @@ -0,0 +1,465 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; +use ieee.numeric_std.all; + +-- CONNECTIVITY DEFINITION +entity bigfile is + port ( + -- from external pins + sysclk : in std_logic; + g_zaq_in : in std_logic_vector(31 downto 0); + g_aux : in std_logic_vector(31 downto 0); + scanb : in std_logic; + g_wrb : in std_logic; + g_rdb : in std_logic; + g_noop_clr : in std_logic_vector(31 downto 0); + swe_ed : in std_logic; + swe_lv : in std_logic; + din : in std_logic_vector(63 downto 0); + g_dout_w0x0f : in std_logic_vector(4 downto 0); + n9_bit_write : in std_logic; + -- from reset_gen block + reset : in std_logic; + alu_u : in std_logic_vector(31 downto 0); + debct_ping : in std_logic; + g_sys_in : out std_logic_vector(31 downto 0); + g_zaq_in_rst_hold : out std_logic_vector(31 downto 0); + g_zaq_hhh_enb : out std_logic_vector(31 downto 0); + g_zaq_out : out std_logic_vector(31 downto 0); + g_dout : out std_logic_vector(31 downto 0); + g_zaq_ctl : out std_logic_vector(31 downto 0); + g_zaq_qaz_hb : out std_logic_vector(31 downto 0); + g_zaq_qaz_lb : out std_logic_vector(31 downto 0); + gwerth : out std_logic_vector(31 downto 0); + g_noop : out std_logic_vector(31 downto 0); + g_vector : out std_logic_vector(8*32-1 downto 0); + swe_qaz1 : out std_logic_vector(31 downto 0) + ); +end bigfile; + + +-- IMPLEMENTATION +architecture rtl of bigfile is + + -- constants + constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000"; + constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001"; + constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010"; + constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011"; + constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100"; + constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101"; + constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110"; + constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111"; + constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000"; + constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001"; + constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010"; + constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011"; + constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100"; + constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101"; + constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110"; + constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111"; + constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000"; + constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001"; + constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010"; + constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011"; + constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100"; + constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101"; + constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110"; + constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111"; + + -- comment + signal g_t_klim_dout : std_logic_vector(31 downto 0); + signal g_t_u_dout : std_logic_vector(31 downto 0); + signal g_t_l_dout : std_logic_vector(31 downto 0); + signal g_t_hhh_l_dout : std_logic_vector(31 downto 0); + signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0); + signal g_secondary_t_l_dout : std_logic_vector(31 downto 0); + signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used + signal g_e_z_dout : std_logic_vector(31 downto 0); + signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0); + signal g_style_vfr_dout : std_logic_vector(31 downto 0); + signal g_style_klim_dout : std_logic_vector(31 downto 0); + signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0); + signal g_style_t_y_dout : std_logic_vector(31 downto 0); + signal g_n_l_dout : std_logic_vector(31 downto 0); + signal g_n_vfr_dout : std_logic_vector(31 downto 0); + signal g_e_n_r_dout : std_logic_vector(31 downto 0); + signal g_n_r_bne_dout : std_logic; + signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0); + signal g_alu_l_dout : std_logic_vector(31 downto 0); + signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0); + signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0); + signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0); + signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0); + signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0); + + -- other + signal q_g_zaq_in : std_logic_vector(31 downto 0); + signal q2_g_zaq_in : std_logic_vector(31 downto 0); + signal q3_g_zaq_in : std_logic_vector(31 downto 0); + signal q_g_zaq_in_cd : std_logic_vector(3 downto 0); + signal q_g_style_vfr_dout : std_logic_vector(31 downto 0); + signal q_g_unzq : std_logic_vector(3 downto 0); + -- i + signal g_n_active : std_logic_vector(31 downto 0); + + -- inter + signal g_zaq_in_y : std_logic_vector(31 downto 0); + signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0); + signal g_zaq_out_i : std_logic_vector(31 downto 0); + signal g_zaq_ctl_i : std_logic_vector(31 downto 0); + signal g_sys_in_i : std_logic_vector(31 downto 0); + signal g_sys_in_ii : std_logic_vector(31 downto 0); + signal g_dout_i : std_logic_vector(31 downto 0); + +begin + + -- qaz out + g_zaq_out_i <= + -- if secondary + (g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or + -- if alu + (g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or + -- otherwise + (not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout); + -- Changed + g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout; + + -- qaz + -- JLB + g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or + (g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i)); + -- mux + --vnavigatoroff + g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000"; + --vnavigatoron + + g_zaq_hhh_enb <= not(g_t_hhh_l_dout); + + g_zaq_qaz_hb <= g_t_qaz_mult_high_dout; + g_zaq_qaz_lb <= g_t_qaz_mult_low_dout; + + + -- Dout + g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else + g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else + g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else + g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else + g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else + g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else + ("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else + g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else + g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else + g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else + g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else + g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else + g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else + g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else + g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else + g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else + ("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else + g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else + g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else + g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else + g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else + gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else + g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else + gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else + "00000000000000000000000000000000"; + g_dout <= g_dout_i when g_rdb = '0' else (others => '1'); + + + -- this can be used to use zzz1 + g_style_main_reset_hold_dout_proc : + process(sysclk) + begin + if( sysclk'event and sysclk = '1' ) then + if( scanb = '1' ) then + if( reset = '1' ) then + g_style_main_reset_hold_dout <= g_zaq_in; + end if; + --vnavigatoroff + else + g_style_main_reset_hold_dout <= q2_g_zaq_in; + end if; + --vnavigatoron + end if; + end process; + -- qaz + g_zaq_in_rst_hold <= g_style_main_reset_hold_dout; + + -- Din + g_doutister_proc : + process(reset, sysclk) + variable g_dout_w0x0f_v : std_logic_vector(4 downto 0); + begin + if( reset /= '0' ) then + g_t_klim_dout <= (others => '0'); + g_t_u_dout <= (others => '0'); + g_t_l_dout <= (others => '0'); + g_t_hhh_l_dout <= (others => '0'); + g_t_jkl_sink_l_dout <= (others => '0'); + g_secondary_t_l_dout <= (others => '0'); + g_style_c_l_dout <= (others => '0'); + g_e_z_dout <= (others => '0'); + g_n_both_qbars_l_dout <= (others => '0'); + g_style_klim_dout <= (others => '0'); + g_style_t_y_dout <= (others => '0'); + g_n_l_dout <= (others => '0'); + g_e_n_r_dout <= (others => '0'); + g_n_r_bne_dout <= '0'; + g_n_div_rebeq_dout <= (others => '1'); + g_alu_l_dout <= (others => '0'); + g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low + g_t_qaz_mult_high_dout <= (others => '0'); + gwerthernal_style_u_dout <= (others => '0'); + gwerthernal_style_l_dout <= (others => '0'); + elsif( sysclk'event and sysclk = '1' ) then + -- clear + g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr; + if( g_wrb = '0' ) then + -- because we now... + for i in 0 to 1 loop + if( i = 0 ) then + g_dout_w0x0f_v := g_dout_w0x0f; + elsif( i = 1 ) then + if( n9_bit_write = '1' ) then + -- set + g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1'; + else + exit; + end if; + --vnavigatoroff + else + -- not possible but added for code coverage's sake + end if; + --vnavigatoron + case g_dout_w0x0f_v is + when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32); + when g_t_u_w0x0f => + -- output klim + for j in 0 to 31 loop + if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then + g_t_u_dout(j) <= din(32*i+j); + end if; + end loop; + when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32); + when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32); + when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32); + when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32); + when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32); + when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32); + when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32); + when g_style_vfr_w0x0f => null; -- read-only register + when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32); + when g_unklimed_style_vfr_w0x0f => null; -- read-only register + when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32); + when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32); + when g_n_vfr_w0x0f => null; -- writes + when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32); + when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32); + when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or + g_n_div_rebeq_dout; -- a '1' writes + when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32); + when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32); + when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32); + when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32); + when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32); + --vnavigatoroff + when others => null; + --vnavigatoron + end case; + end loop; + + end if; + end if; + end process; + + -- sample + g_zaq_in_sample_proc : + process(reset, sysclk) + begin + if( reset /= '0' ) then + q_g_zaq_in <= (others => '0'); + q2_g_zaq_in <= (others => '0'); + q3_g_zaq_in <= (others => '0'); + elsif( sysclk'event and sysclk = '1' ) then + q_g_zaq_in <= g_zaq_in; + q2_g_zaq_in <= q_g_zaq_in; + q3_g_zaq_in <= g_zaq_in_y; + end if; + end process; + + -- vfr register + g_unklimed_style_vfr_dout <= q2_g_zaq_in; + + -- switch + g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in; + + -- qaz + g_style_vfr_dout <= -- top 2 + (g_zaq_in_y(31 downto 4) & + -- FSM + (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or + -- otherwise just use + (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0)))); + + -- in scan mode + g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1' + --vnavigatoroff + else g_style_t_y_dout; + --vnavigatoron + + g_sys_in_i <= (-- top 28 + (g_zaq_in_y_no_dout(31 downto 4) & + -- is enabled + (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or + -- otherwise just use + (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0))))); + + g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout ); + + g_sys_in <= g_sys_in_ii; + + lpq_proc : + process(reset, sysclk) + begin + if( reset /= '0' ) then + q_g_zaq_in_cd <= (others => '0'); + q_g_unzq <= (others => '1'); + elsif( sysclk'event and sysclk = '1' ) then + -- sample + if( debct_ping = '1') then + -- taken + for i in 0 to 3 loop + if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then + q_g_unzq(i) <= '1'; + else + if( q_g_unzq(i) = '0' ) then + q_g_zaq_in_cd(i) <= g_zaq_in_y(i); + else + q_g_unzq(i) <= '0'; + end if; + end if; + end loop; + else + for i in 0 to 3 loop + if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then + q_g_unzq(i) <= '1'; + end if; + end loop; + end if; + end if; + end process; + + -- generate lqqs + sample_forwerth_proc : + process(reset, sysclk) + begin + if( reset /= '0' ) then + q_g_style_vfr_dout <= (others => '0'); + elsif( sysclk'event and sysclk = '1' ) then + if( scanb = '1' ) then + q_g_style_vfr_dout <= g_style_vfr_dout; + --vnavigatoroff + else + -- in scan + q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii; + end if; + --vnavigatoron + end if; + end process; + + -- generate + g_n_active <= -- 1 to 0 + (((q_g_style_vfr_dout and not g_style_vfr_dout) or + -- get this + (not q_g_style_vfr_dout and g_style_vfr_dout and + g_n_both_qbars_l_dout))) and + -- must be + g_n_l_dout; + + -- check for lqq active and set lqq vfr register + -- also clear + n_proc : + process(reset, sysclk) + begin + if( reset /= '0' ) then + g_n_vfr_dout <= (others => '0'); + gwerth <= (others => '0'); + elsif( sysclk'event and sysclk = '1' ) then + for i in 0 to 31 loop + -- lqq + -- vfr matches + if( g_n_active(i) = '1' ) then + gwerth(i) <= '1'; + if( g_e_z_dout(i) = '1' ) then + -- lqq + g_n_vfr_dout(i) <= '1'; + else + g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); + end if; + else + -- clear + if( g_e_z_dout(i) = '0' ) then + g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign + -- in both + if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then + gwerth(i) <= '0'; + end if; + else + -- write + if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then + gwerth(i) <= '0'; + g_n_vfr_dout(i) <= '0'; + end if; + end if; + end if; + end loop; + end if; + end process; + + ---- + -- Create the Lqq + createwerth_vec_proc : + process( g_n_r_bne_dout, g_e_n_r_dout) + variable imod8, idiv8 : integer; + begin + for i in 0 to 31 loop + imod8 := i mod 8; + idiv8 := i / 8; + + if( g_n_r_bne_dout = '0' ) then + -- non-unique + g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); + else + -- unique + if( imod8 = 0 ) then + g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8); + else + g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) + + to_unsigned(imod8, 8)); + end if; + end if; + end loop; + end process; + + ---- + -- Qaz + g_noop <= g_n_div_rebeq_dout; + + + create_g_ack_bne_proc : + process( swe_ed,swe_lv,g_e_z_dout) + begin + for i in 0 to 31 loop + if( g_e_z_dout(i) = '1') then + swe_qaz1(i) <= swe_ed; + else + swe_qaz1(i) <= swe_lv; + end if; + end loop; + end process; + +end rtl; diff --git a/examples/clk.vhd b/examples/clk.vhd new file mode 100644 index 0000000..81372d9 --- /dev/null +++ b/examples/clk.vhd @@ -0,0 +1,36 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic; + ival : in std_logic_vector(31 downto 0) + ); +end clk; +architecture rtl of clk is + signal foo : std_logic_vector(10+3 downto 0); + signal baz : std_logic_vector(2 downto 0); + signal egg : std_logic_vector(4 to 7-1); +begin + pfoo: process(reset, sysclk) + begin + if( reset /= '0' ) then + foo <= (others => '1'); + elsif( sysclk'event and sysclk = '1' ) then + foo <= ival(31 downto 31-(10+3)); + end if; + end process; + pbaz: process(preset, dsysclk) + begin + if( preset /= '1' ) then + baz <= (others => '0'); + elsif( dsysclk'event and dsysclk = '0' ) then + baz <= ival(2 downto 0); + end if; + end process; + pegg: process(qreset, esysclk) + begin + if( qreset /= '1' ) then + egg <= (others => '0'); + elsif( esysclk'event and esysclk = '0' ) then + egg <= ival(6 downto 4); + end if; + end process; +end rtl; diff --git a/examples/counters.vhd b/examples/counters.vhd new file mode 100644 index 0000000..044a9c5 --- /dev/null +++ b/examples/counters.vhd @@ -0,0 +1,348 @@ +library IEEE; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counters is + port( + sysclk : in std_logic; + foo_card : in std_logic; + wfoo0_baz : in std_logic; + wfoo0_blrb : in std_logic; + wfoo0_zz1pb : in std_logic; + wfoo0_turn : in std_logic_vector(31 downto 0); + debct_baz : in std_logic; + debct_blrb : in std_logic; + debct_zz1pb : in std_logic; + debct_bar : in std_logic; + debct_turn : in std_logic_vector(31 downto 0); + Z0_bar : in std_logic; + Z0_baz : in std_logic; + Z0_blrb : in std_logic; + Z0_zz1pb : in std_logic; + Z0_turn : in std_logic_vector(31 downto 0); + Y1_bar : in std_logic; + Y1_baz : in std_logic; + Y1_blrb : in std_logic; + Y1_zz1pb : in std_logic; + Y1_turn : in std_logic_vector(31 downto 0); + X2_bar : in std_logic; + X2_baz : in std_logic; + X2_blrb : in std_logic; + X2_zz1pb : in std_logic; + X2_turn : in std_logic_vector(31 downto 0); + W3_bar : in std_logic; + W3_baz : in std_logic; + W3_blrb : in std_logic; + W3_zz1pb : in std_logic; + W3_turn : in std_logic_vector(31 downto 0); + -- to engine block + Z0_cwm : out std_logic; + Z0 : out std_logic_vector(31 downto 0); + Y1_cwm : out std_logic; + Y1 : out std_logic_vector(31 downto 0); + X2_cwm : out std_logic; + X2 : out std_logic_vector(31 downto 0); + W3_cwm : out std_logic; + W3 : out std_logic_vector(31 downto 0); + wfoo0_cwm : out std_logic; + wfoo0_llwln : out std_logic_vector(31 downto 0); + debct_cwm : out std_logic; + debct_pull : out std_logic; + debct : out std_logic_vector(31 downto 0); + wdfilecardA2P : out std_logic + ); +end counters; + + +architecture rtl of counters is + + signal wfoo0_llwln_var : unsigned(31 downto 0); + signal debct_var : unsigned(31 downto 0); + signal Z0_var : unsigned(31 downto 0); + signal Y1_var : unsigned(31 downto 0); + signal X2_var : unsigned(31 downto 0); + signal W3_var : unsigned(31 downto 0); + signal main_wfoo0_cwm : std_logic; + signal do_q3p_Z0 : std_logic; + signal do_q3p_Y1 : std_logic; + signal do_q3p_X2 : std_logic; + signal do_q3p_W3 : std_logic; + signal do_q3p_wfoo0 : std_logic; + signal do_q3p_debct : std_logic; + + signal Z0_cwm_i : std_logic; + signal Y1_cwm_i : std_logic; + signal X2_cwm_i : std_logic; + signal W3_cwm_i : std_logic; + signal debct_cwm_i : std_logic; + + signal file_card_i : std_logic; + signal do_file_card_i : std_logic; + signal prev_do_file_card : std_logic; + + +begin + + ----- + -- form the outputs + wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var); + debct <= std_logic_vector(debct_var); + Z0 <= std_logic_vector(Z0_var); + Y1 <= std_logic_vector(Y1_var); + X2 <= std_logic_vector(X2_var); + W3 <= std_logic_vector(W3_var); + Z0_cwm <= Z0_cwm_i; + Y1_cwm <= Y1_cwm_i; + X2_cwm <= X2_cwm_i; + W3_cwm <= W3_cwm_i; + debct_cwm <= debct_cwm_i; + + wdfilecardA2P <= do_file_card_i; + + LLWLNS : + process(foo_card, sysclk) + begin + if foo_card = '1' then + wfoo0_llwln_var <= (others => '0'); + debct_var <= (others => '0'); + Z0_var <= (others => '0'); + Y1_var <= (others => '0'); + X2_var <= (others => '0'); + W3_var <= (others => '0'); + + wfoo0_cwm <= '0'; + debct_cwm_i <= '0'; + debct_pull <= '0'; + Z0_cwm_i <= '0'; + Y1_cwm_i <= '0'; + X2_cwm_i <= '0'; + W3_cwm_i <= '0'; + main_wfoo0_cwm <= '0'; + file_card_i <= '0'; + + do_q3p_wfoo0 <= '0'; + do_file_card_i <= '0'; + prev_do_file_card <= '0'; + + do_q3p_Z0 <= '0'; + do_q3p_Y1 <= '0'; + do_q3p_X2 <= '0'; + do_q3p_W3 <= '0'; + do_q3p_debct <= '0'; + + else + if sysclk'event and sysclk = '1' then + + -- pull + debct_pull <= '0'; + do_file_card_i <= '0'; + + ---- + -- wfoo0 + + if wfoo0_baz = '1' then + wfoo0_llwln_var <= unsigned(wfoo0_turn); + main_wfoo0_cwm <= '0'; + if wfoo0_llwln_var = "00000000000000000000000000000000" then + do_q3p_wfoo0 <= '0'; + else + do_q3p_wfoo0 <= '1'; + end if; + else + if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then + wfoo0_llwln_var <= wfoo0_llwln_var - 1; + if (wfoo0_llwln_var = "00000000000000000000000000000000") then + wfoo0_llwln_var <= unsigned(wfoo0_turn); + if main_wfoo0_cwm = '0' then + wfoo0_cwm <= '1'; + main_wfoo0_cwm <= '1'; + else + do_file_card_i <= '1'; + do_q3p_wfoo0 <= '0'; + end if; + end if; + end if; + end if; + + if wfoo0_zz1pb = '0' then + wfoo0_cwm <= '0'; + end if; + + if Z0_baz = '1' then -- counter Baz + Z0_var <= unsigned(Z0_turn); + if Z0_turn = "00000000000000000000000000000000" then + do_q3p_Z0 <= '0'; + else + do_q3p_Z0 <= '1'; + end if; + else + if do_q3p_Z0 = '1' and Z0_blrb = '1' then + if Z0_bar = '0' then + if Z0_cwm_i = '0' then + if do_q3p_Z0 = '1' then + Z0_var <= Z0_var - 1; + if (Z0_var = "00000000000000000000000000000001") then + Z0_cwm_i <= '1'; + do_q3p_Z0 <= '0'; + end if; + end if; + end if; + else + Z0_var <= Z0_var - 1; + if (Z0_var = "00000000000000000000000000000000") then + Z0_cwm_i <= '1'; + Z0_var <= unsigned(Z0_turn); + end if; + end if; -- Z0_bar + end if; + end if; -- Z0_blrb + + if Z0_zz1pb = '0' then + Z0_cwm_i <= '0'; + end if; + + if Y1_baz = '1' then -- counter Baz + Y1_var <= unsigned(Y1_turn); + if Y1_turn = "00000000000000000000000000000000" then + do_q3p_Y1 <= '0'; + else + do_q3p_Y1 <= '1'; + end if; + elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then + if Y1_bar = '0' then + if Y1_cwm_i = '0' then + if do_q3p_Y1 = '1' then + Y1_var <= Y1_var - 1; + if (Y1_var = "00000000000000000000000000000001") then + Y1_cwm_i <= '1'; + do_q3p_Y1 <= '0'; + end if; + end if; + end if; + else + Y1_var <= Y1_var - 1; + + if (Y1_var = "00000000000000000000000000000000") then + Y1_cwm_i <= '1'; + Y1_var <= unsigned(Y1_turn); + end if; + end if; -- Y1_bar + + end if; -- Y1_blrb + + if Y1_zz1pb = '0' then + Y1_cwm_i <= '0'; + end if; + + if X2_baz = '1' then -- counter Baz + X2_var <= unsigned(X2_turn); + if X2_turn = "00000000000000000000000000000000" then + do_q3p_X2 <= '0'; + else + do_q3p_X2 <= '1'; + end if; + elsif do_q3p_X2 = '1' and X2_blrb = '1' then + if X2_bar = '0' then + if X2_cwm_i = '0' then + if do_q3p_X2 = '1' then + X2_var <= X2_var - 1; + if (X2_var = "00000000000000000000000000000001") then + X2_cwm_i <= '1'; + do_q3p_X2 <= '0'; + end if; + end if; + end if; + else + X2_var <= X2_var - 1; + + if (X2_var = "00000000000000000000000000000000") then --{ + X2_cwm_i <= '1'; + X2_var <= unsigned(X2_turn); + end if; + end if; --X2_bar + end if; -- X2_blrb + + if X2_zz1pb = '0' then + X2_cwm_i <= '0'; + end if; + + + if W3_baz = '1' then -- counter Baz + W3_var <= unsigned(W3_turn); + if W3_turn = "00000000000000000000000000000000" then + do_q3p_W3 <= '0'; + else + do_q3p_W3 <= '1'; + end if; + elsif do_q3p_W3 = '1' and W3_blrb = '1' then + if W3_bar = '0' then + if W3_cwm_i = '0'then + if do_q3p_W3 = '1' then + W3_var <= W3_var - 1; + if (W3_var = "00000000000000000000000000000001") then + W3_cwm_i <= '1'; + do_q3p_W3 <= '0'; + end if; + end if; + end if; + else + W3_var <= W3_var - 1; + + if (W3_var = "00000000000000000000000000000000") then --{ + W3_cwm_i <= '1'; + W3_var <= unsigned(W3_turn); + end if; + end if; -- W3_bar + + end if; -- W3_blrb + + if W3_zz1pb = '0' then + W3_cwm_i <= '0'; + end if; + + if debct_baz = '1' then -- counter Baz + debct_var <= unsigned(debct_turn); + if debct_turn = "00000000000000000000000000000000" then + do_q3p_debct <= '0'; + else + do_q3p_debct <= '1'; + end if; + elsif do_q3p_debct = '1' and debct_blrb = '1' then + if debct_bar = '0' then + if debct_cwm_i = '0'then + if do_q3p_debct = '1' then + debct_var <= debct_var - 1; + if (debct_var = "00000000000000000000000000000001") then + debct_cwm_i <= '1'; + debct_pull <= '1'; + do_q3p_debct <= '0'; + end if; + end if; + end if; + else + ---- T + -- Continue + debct_var <= debct_var - 1; + + -- ending + if (debct_var = "00000000000000000000000000000000") then --{ + debct_cwm_i <= '1'; + debct_pull <= '1'; + debct_var <= unsigned(debct_turn); + end if; + end if; -- debct_bar + + end if; -- debct_blrb + + + -- comment + if debct_zz1pb = '0' then + debct_cwm_i <= '0'; + end if; + + end if; + end if; + end process; + +end rtl; diff --git a/examples/expr.vhd b/examples/expr.vhd new file mode 100644 index 0000000..24b3885 --- /dev/null +++ b/examples/expr.vhd @@ -0,0 +1,40 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; +use ieee.numeric_std.all; + +entity expr is port( reset, sysclk, ival : in std_logic); +end expr; +architecture rtl of expr is + signal foo : std_logic_vector(13 downto 0); + signal baz : std_logic_vector(2 downto 0); + signal bam : std_logic_vector(22 downto 0); + signal out_i : std_logic_vector(5 downto 3); + signal input_status : std_logic_vector(8 downto 0); + signal enable, debug, aux, outy, dv, value : std_logic; +begin + -- drive input status + input_status <= -- top bits + (foo(9 downto 4) & + (( baz(3 downto 0) and foo(3 downto 0) or + (not baz(3 downto 0) and bam(3 downto 0))))); + -- drive based on foo + out_i <= + -- if secondary enabl is set then drive aux out + (enable and (aux xor outy)) or + -- if debug is enabled + (debug and dv and not enable) or + -- otherwise we drive reg + (not debug and not enable and value); + -- not drive + + pfoo: process(reset, sysclk) + begin + if( reset /= '0' ) then + foo <= (others => '0'); + elsif( sysclk'event and sysclk = '0' ) then + foo(3*(2-1)) <= (4*(1+2)); + bam(foo'range) <= foo; + end if; + end process; +end rtl; diff --git a/examples/for.vhd b/examples/for.vhd new file mode 100644 index 0000000..796f209 --- /dev/null +++ b/examples/for.vhd @@ -0,0 +1,38 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; +use ieee.numeric_std.all; +entity forp is port( + reset, sysclk : in std_logic +); +end forp; +architecture rtl of forp is + + signal selection : std_logic; + signal egg_timer : std_logic_vector(6 downto 0); +begin + TIMERS : + process(reset, sysclk) + variable timer_var : integer:= 0; + variable a, i, j, k : integer; + variable zz5 : std_logic_vector(31 downto 0); + variable zz : std_logic_vector(511 downto 0); + begin + if reset = '1' then + selection <= '1'; + timer_var := 2; + egg_timer <= (others => '0'); + elsif sysclk'event and sysclk = '1' then + -- pulse only lasts for once cycle + selection <= '0'; + egg_timer <= (others => '1'); + for i in 0 to j*k loop + a := a + i; + for k in a-9 downto -14 loop + zz5 := zz(31+k downto k); + end loop; -- k + end loop; -- i + end if; + end process; + +end rtl; diff --git a/examples/generate.vhd b/examples/generate.vhd new file mode 100644 index 0000000..56d5d3c --- /dev/null +++ b/examples/generate.vhd @@ -0,0 +1,50 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +entity gen is generic( + bus_width : integer := 15; + TOP_GP2 : integer:= 0 + ); + port( + sysclk, reset, wrb : in std_logic; + din : in std_logic_vector(bus_width downto 0); + rdout: out std_logic_vector(bus_width downto 0) + +); +end gen; +architecture rtl of gen is + component wbit1 -- register bit default 1 + port( + clk : in std_logic; + wrb : in std_logic; + reset : in std_logic; + enb : in std_logic; + din : in std_logic; + dout : out std_logic); + end component; + + signal regSelect : std_logic_vector(bus_width * 2 downto 0); +begin + ----------------------------------------------------- + -- Reg : GP 2 + -- Active : 32 + -- Type : RW + ----------------------------------------------------- + reg_gp2 : for bitnum in 0 to bus_width generate + wbit1_inst : wbit1 + PORT MAP( + clk => sysclk, + wrb => wrb, + reset => reset, + enb => regSelect(TOP_GP2), + din => din(bitnum), + dout => rdout(bitnum) + ); + end generate; + + process(sysclk) begin + if sysclk'event and sysclk = '1' then + regSelect(1) <= '1'; + end if; + end process; + +end rtl; diff --git a/examples/generic.vhd b/examples/generic.vhd new file mode 100644 index 0000000..6ffc208 --- /dev/null +++ b/examples/generic.vhd @@ -0,0 +1,32 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +entity test is + generic( + dog_width : std_logic_vector(7 downto 0) := "10101100"; + bus_width : integer := 32 + ); + port( reset, sysclk : in std_logic; + a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) + ); +end test; +architecture rtl of test is + signal foo : std_logic_vector(1+1 downto 0); + signal code,code1: std_logic_vector(9 downto 0); + signal egg : std_logic_vector(324 to 401); + signal baz : std_logic_vector(bus_width*3-1 to bus_width*4); + signal complex : std_logic_vector(31 downto 0); +begin + -- Example of with statement + with foo(2 downto 0) select + code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110", + "11100010" when "101", + (others => '1') when "010", + (others => '0') when "011", + a + b + '1' when others; + code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); + + foo <= (others => '0'); + egg <= (others => '0'); + baz <= (others => '1'); + complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001"; +end rtl; diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd new file mode 100644 index 0000000..0ddd610 --- /dev/null +++ b/examples/genericmap.vhd @@ -0,0 +1,79 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +entity test is +generic( + rst_val : std_logic := '0'; + thing_size: integer := 201; + bus_width : integer := 201 mod 32); +port( + clk, rstn : in std_logic; + en, start_dec : in std_logic; + addr : in std_logic_vector(2 downto 0); + din : in std_logic_vector(25 downto 0); + we : in std_logic; + pixel_in : in std_logic_vector(7 downto 0); + pix_req : in std_logic; + config, bip : in std_logic; + a, b : in std_logic_vector(7 downto 0); + c, load : in std_logic_vector(7 downto 0); + pack : in std_logic_vector(6 downto 0); + base : in std_logic_vector(2 downto 0); + qtd : in std_logic_vector(21 downto 0); + -- Outputs + dout : out std_logic_vector(25 downto 0); + pixel_out : out std_logic_vector(7 downto 0); + pixel_valid : out std_logic; + code : out std_logic_vector(9 downto 0); + complex : out std_logic_vector(23 downto 0); + eno : out std_logic +); +end test; +architecture rtl of test is + + component dsp + generic( + rst_val : std_logic := '0'; + thing_size: integer := 201; + bus_width : integer := 22); + port( + -- Inputs + clk, rstn : in std_logic; + -- Outputs + dout : out std_logic_vector(bus_width downto 0); + memaddr : out std_logic_vector(5 downto 0); + memdout : out std_logic_vector(13 downto 0) + ); + end component; + signal param : std_logic_vector(7 downto 0); + signal selection : std_logic; + signal start, enf : std_logic; -- Start and enable signals + signal memdin : std_logic_vector(13 downto 0); + signal memaddr : std_logic_vector(5 downto 0); + signal memdout : std_logic_vector(13 downto 0); + signal colour : std_logic_vector(1 downto 0); +begin + dsp_inst0 : dsp + port map( + -- Inputs + clk => clk, + rstn => rstn, + -- Outputs + dout => dout, + memaddr => memaddr, + memdout => memdout + ); + + dsp_inst1 : dsp + generic map( + rst_val => '1', + bus_width => 16) + port map( + -- Inputs + clk => clk, + rstn => rstn, + -- Outputs + dout => dout, + memaddr => memaddr, + memdout => memdout + ); +end rtl; diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd new file mode 100644 index 0000000..161ba34 --- /dev/null +++ b/examples/ifchain.vhd @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +entity test is port( + clk, rstn : in std_logic +); +end test; +architecture rtl of test is + signal a : std_logic_vector(3 downto 0); + signal b : std_logic_vector(3 downto 0); + signal status : std_logic; +begin + process(clk) begin + if clk'event and clk = '1' then + if b(1) & a(3 downto 2) = "001" then + status <= "1"; + end if; + end if; + end process; + +end rtl; diff --git a/examples/test.vhd b/examples/test.vhd new file mode 100644 index 0000000..0532a7b --- /dev/null +++ b/examples/test.vhd @@ -0,0 +1,191 @@ +-- Project: VHDL to Verilog RTL translation +-- Revision: 1.0 +-- Date of last Revision: February 27 2001 +-- Designer: Vincenzo Liguori +-- vhd2vl test file +-- This VHDL file exercises vhd2vl + +LIBRARY IEEE; + +USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; + +entity test is port( + -- Inputs + clk, rstn : in std_logic; + en, start_dec : in std_logic; + addr : in std_logic_vector(2 downto 0); + din : in std_logic_vector(25 downto 0); + we : in std_logic; + pixel_in : in std_logic_vector(7 downto 0); + pix_req : in std_logic; + config, bip : in std_logic; + a, b : in std_logic_vector(7 downto 0); + c, load : in std_logic_vector(7 downto 0); + pack : in std_logic_vector(6 downto 0); + base : in std_logic_vector(2 downto 0); + qtd : in std_logic_vector(21 downto 0); + -- Outputs + dout : out std_logic_vector(25 downto 0); + pixel_out : out std_logic_vector(7 downto 0); + pixel_valid : out std_logic; + code : out std_logic_vector(9 downto 0); + code1 : out std_logic_vector(9 downto 0); + complex : out std_logic_vector(23 downto 0); + eno : out std_logic +); +end test; + +architecture rtl of test is + +-- Components declarations are ignored by vhd2vl +-- but they are still parsed + +component dsp port( + -- Inputs + clk, rstn : in std_logic; + en, start : in std_logic; + param : in std_logic_vector(7 downto 0); + addr : in std_logic_vector(2 downto 0); + din : in std_logic_vector(25 downto 0); + we : in std_logic; + memdin : out std_logic_vector(13 downto 0); + -- Outputs + dout : out std_logic_vector(25 downto 0); + memaddr : out std_logic_vector(5 downto 0); + memdout : out std_logic_vector(13 downto 0) +); +end component; + +component mem port( + -- Inputs + clk, rstn : in std_logic; + en : in std_logic; + cs : in std_logic; + addr : in std_logic_vector(5 downto 0); + din : in std_logic_vector(13 downto 0); + -- Outputs + dout : out std_logic_vector(13 downto 0) +); +end component; + + type state is (red, green, blue, yellow); + signal status : state; + constant PARAM1 : std_logic_vector(7 downto 0):="01101101"; + constant PARAM2 : std_logic_vector(7 downto 0):="11001101"; + constant PARAM3 : std_logic_vector(7 downto 0):="00010111"; + signal param : std_logic_vector(7 downto 0); + signal selection : std_logic; + signal start, enf : std_logic; -- Start and enable signals + signal memdin : std_logic_vector(13 downto 0); + signal memaddr : std_logic_vector(5 downto 0); + signal memdout : std_logic_vector(13 downto 0); + signal colour : std_logic_vector(1 downto 0); +begin + + param <= PARAM1 when config = '1' else PARAM2 when status = green else PARAM3; + + -- Synchronously process + process(clk) begin + if clk'event and clk = '1' then + pixel_out <= pixel_in xor "11001100"; + end if; + end process; + + -- Synchronous process + process(clk) begin + if rising_edge(clk) then + case status is + when red => colour <= "00"; + when green => colour <= "01"; + when blue => colour <= "10"; + when others => colour <= "11"; + end case; + end if; + end process; + + -- Synchronous process with asynch reset + process(clk,rstn) begin + if rstn = '0' then + status <= red; + elsif rising_edge(clk) then + case status is + when red => + if pix_req = '1' then + status <= green; + end if; + when green => + if a(3) = '1' then + start <= start_dec; + status <= blue; + elsif (b(5) & a(3 downto 2)) = "001" then + status <= yellow; + end if; + when blue => + status <= yellow; + when others => + start <= '0'; + status <= red; + end case; + end if; + end process; + + -- Example of with statement + with memaddr(2 downto 0) select + code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110", + "11100010" when "101", + (others => '1') when "010", + (others => '0') when "011", + a + b + '1' when others; + code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); + + -- Asynch process + decode : process(we, addr, config, bip) begin + if we = '1' then + if addr(2 downto 0) = "100" then + selection <= '1'; + elsif (b & a) = a & b and bip = '0' then + selection <= config; + else + selection <= '1'; + end if; + else + selection <= '0'; + end if; + end process decode; + + -- Components instantiation + dsp_inst : dsp port map( + -- Inputs + clk => clk, + rstn => rstn, + en => en, + start => start, + param => param, + addr => addr, + din => din, + we => we, + memdin => memdin, + -- Outputs + dout => dout, + memaddr => memaddr, + memdout => memdout + ); + + dsp_mem : mem port map( + -- Inputs + clk => clk, + rstn => rstn, + en => en, + cs => selection, + addr => memaddr, + din => memdout, + -- Outputs + dout => memdin + ); + + complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001"; + + enf <= '1' when a = "1101111" + load and c < "1000111" else '0'; + eno <= enf; + +end rtl; diff --git a/src/def.h b/src/def.h new file mode 100644 index 0000000..b7ecd8d --- /dev/null +++ b/src/def.h @@ -0,0 +1,78 @@ +/* + vhd2vl v2.2 + VHDL to Verilog RTL translator + Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com + Modifications (C) 2006 Mark Gonzales - PMC Sierra Inc + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +#ifndef __def_h +#define __def_h + +#define MAXINDENT 36 +#define MAXEDGES 1000 /* maximum number of @(edge) processes supported in a source file */ +typedef struct signal { + char *name; /* Signal name */ + int reg; /* Verilog reg */ + struct signal *next; +} signal; + +typedef struct nlist { + char *name; /* Name */ + struct nlist *next; +} nlist; + +typedef struct slist { + unsigned int type; + struct slist *slst; + union { + struct slist *sl; /* type 0 */ + char *txt; /* type 1 */ + char **ptxt; /* type 3!*/ + int val; /* type 2,4 */ + } data; +} slist; + +enum vrangeType {tSCALAR, tSUBSCRIPT, tVRANGE}; +typedef struct vrange { + /* int hi, lo; */ + enum vrangeType vtype; + struct slist *nhi, *nlo; /* MAG index is a simple expression */ + slist *size_expr; /* expression that calculates size (width) of this vrange */ + int sizeval; /* precalculated size value */ +} vrange; + +typedef struct slval { + slist *sl; + int val; /* Signal size */ + vrange *range; /* Signal size */ +} slval; + +typedef struct expdata { + char op; + int value; /* only set for simple_expr */ + slist *sl; +} expdata; + +typedef struct sglist { + char *name; /* Signal name */ + char *type; /* Reg or wire */ + vrange *range; /* Signal size */ + struct sglist *next; +} sglist; + + +#endif diff --git a/src/makefile b/src/makefile new file mode 100644 index 0000000..81e58e7 --- /dev/null +++ b/src/makefile @@ -0,0 +1,11 @@ +vhd2vl : lex.yy.c vhd2vl.tab.c + gcc -Wall -Wshadow -W -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl + +vhd2vl.tab.c : vhd2vl.y + bison -d -v -t vhd2vl.y + +lex.yy.c : vhd2vl.l + flex -i vhd2vl.l + +clean : + rm -f lex.yy.c vhd2vl.tab.c vhd2vl.tab.h vhd2vl.output vhd2vl diff --git a/src/vhd2vl.l b/src/vhd2vl.l new file mode 100644 index 0000000..3fa9675 --- /dev/null +++ b/src/vhd2vl.l @@ -0,0 +1,170 @@ +/* + vhd2vl v2.2 + VHDL to Verilog RTL translator + Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com + Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc + Modifications Copyright (C) 2008, 2009 Larry Doolittle - LBNL + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +%option noinput +%option nounput + +%{ +#include <stdio.h> +#include <string.h> +#include "def.h" +#include "vhd2vl.tab.h" + +extern int lineno; + +extern int skipRem; + +void getstring(int skip); +void getbasedstring(int skip); + +%} +%% + +[ \t] {;} + +"--".*\n { + if (skipRem == 0) { + /* sometimes comments should be dropped by lex - + * e.g. in expressions - this makes the grammar much simpler + */ + yylval.txt=malloc(strlen(yytext)+1); + strcpy(yylval.txt, yytext); + yylval.txt[0]='/'; + yylval.txt[1]='/'; + lineno++; + return REM; + } else { + lineno++; + } +} +"library ".*\n {lineno++;} +"use ".*\n {lineno++;} + +"\x0d\n" | +\n { lineno++;} + +"entity" { return ENTITY; } +"is" { return IS; } +"port" { return PORT; } +"generic" { return GENERIC; } +"map" { return MAP; } +"in" { return IN; } +"out" { return OUT; } +"inout" { return INOUT; } +"time" | +"natural" | +"positive" | +"integer" { return INTEGER; } +"boolean" | +"std_logic" | +"std_ulogic" { return BIT; } +"signed" | +"unsigned" | +"std_logic_vector" | +"std_ulogic_vector" { return BITVECT; } +"downto" { return DOWNTO; } +"to" { return TO; } +"type" {return TYPE; } +"end" { return END; } +"for" { return FOR; } +"loop" { return LOOP; } +"generate" { return GENERATE; } +"architecture" { return ARCHITECTURE; } +"component" { return COMPONENT; } +"of" { return OF; } +"signal" { return SIGNAL; } +"begin" { return BEGN; } +"not" { return NOT; } +"when" { return WHEN; } +"exit" { return EXIT; } +"with" { + return WITH; } +"select" { return SELECT; } +"others" { return OTHERS; } +"range" { return RANGE; } +"process" { return PROCESS; } +"variable" { return VARIABLE; } +"constant" { return CONSTANT; } +"null" { return NULLV; } +"if" { return IF; } +"then" { return THEN; } +"elsif" { return ELSIF; } +"else" { return ELSE; } +"case" { return CASE; } +"after" { return AFTER; } +"and" { return AND; } +"or" { return OR; } +"xor" { return XOR; } +"xnor" { return XNOR; } +"mod" { return MOD; } +"event" { return EVENT; } +"rising_edge" { return POSEDGE;} +"falling_edge" { return NEGEDGE;} +"resize" { return CONVFUNC_2;} +"to_unsigned" { return CONVFUNC_2;} + +\"[ \!#-~]*\" | +\'[01xz]\' { getstring(1); return STRING;} + +#[0-9a-f]*# { + getbasedstring(1); /* skip leading # */ + return BASED; +} + +[a-zA-Z_$][a-zA-Z0-9_$.]* { + yylval.txt=malloc(strlen(yytext)+1); + strcpy(yylval.txt, yytext); + return NAME; +} + +[0-9]+ { + sscanf(yytext, "%d", &yylval.n); + return NATURAL; +} + +. { return yytext[0]; } + +%% + +void getstring(int skip){ +/* Gets a string excluding " or ' */ +int i; + + for(i=skip; yytext[i]!='"' && yytext[i]!='\'' && yytext[i]!=0; i++); + yytext[i]=0; + yylval.txt=malloc(i+1); + strcpy(yylval.txt, yytext+skip); +} + +void getbasedstring(int skip){ +/* Gets a string excluding # */ +int i; + + for(i=skip; yytext[i]!='#' && yytext[i]!=0; i++); + yytext[i]=0; + yylval.txt=malloc(i+1); + strcpy(yylval.txt, yytext+skip); +} + +void yyerror(char *s){ + fprintf(stderr,"%s at \"%s\" in line %d.\n\n",s,yytext,lineno); +} diff --git a/src/vhd2vl.y b/src/vhd2vl.y new file mode 100644 index 0000000..f672df5 --- /dev/null +++ b/src/vhd2vl.y @@ -0,0 +1,2145 @@ +/* + vhd2vl v2.2 + VHDL to Verilog RTL translator + Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com + Modifications (C) 2006 Mark Gonzales - PMC Sierra Inc + Modifications (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +%{ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <assert.h> +#include "def.h" + +int yylex(void); +void yyerror(char *s); + +/* You will of course want to tinker with this if you use a debugging + * malloc(), otherwise all the line numbers will point here. + */ +void *xmalloc(size_t size) { + void *p = malloc(size); + if (!p) { + perror("malloc"); + exit(2); + } + return p; +} + +int skipRem = 0; +int lineno=1; + +sglist *io_list=NULL; +sglist *sig_list=NULL; +sglist *type_list=NULL; + +/* need a stack of clock-edges because all edges are processed before all processes are processed. + * Edges are processed in source file order, processes are processed in reverse source file order. + * The original scheme of just one clkedge variable makes all clocked processes have the edge sensitivity + * of the last clocked process in the file. + */ +int clkedges[MAXEDGES]; +int clkptr = 0; +int delay=1; +int dolist=1; +int np=1; +char wire[]="wire"; +char reg[]="reg"; +int dowith=0; +slist *slwith; + +/* Indentation variables */ +int indent=0; +slist *indents[MAXINDENT]; + +void fslprint(FILE *fp,slist *sl){ + if(sl){ + assert(sl != sl->slst); + fslprint(fp,sl->slst); + switch(sl->type){ + case 0 : + assert(sl != sl->data.sl); + fslprint(fp,sl->data.sl); + break; + case 1 : case 4 : + fprintf(fp,"%s",sl->data.txt); + break; + case 2 : + fprintf(fp,"%d",sl->data.val); + break; + case 3 : + fprintf(fp,"%s",*(sl->data.ptxt)); + break; + } + } +} + +void slprint(slist *sl){ + fslprint(stdout, sl); +} + +slist *copysl(slist *sl){ + if(sl){ + slist *newsl; + newsl = xmalloc(sizeof(slist)); + *newsl = *sl; + if (sl->slst != NULL) { + assert(sl != sl->slst); + newsl->slst = copysl(sl->slst); + } + switch(sl->type){ + case 0 : + if (sl->data.sl != NULL) { + assert(sl != sl->data.sl); + newsl->data.sl = copysl(sl->data.sl); + } + break; + case 1 : case 4 : + newsl->data.txt = xmalloc(strlen(sl->data.txt) + 1); + strcpy(newsl->data.txt, sl->data.txt); + break; + } + return newsl; + } + return NULL; +} + +slist *addtxt(slist *sl, char *s){ + slist *p; + + if(s == NULL) + return sl; + p = xmalloc(sizeof *p); + p->type = 1; + p->slst = sl; + p->data.txt = xmalloc(strlen(s) + 1); + strcpy(p->data.txt, s); + + return p; +} + +slist *addothers(slist *sl, char *s){ + slist *p; + + if(s == NULL) + return sl; + p = xmalloc(sizeof *p); + p->type = 4; + p->slst = sl; + p->data.txt = xmalloc(strlen(s) + 1); + strcpy(p->data.txt, s); + + return p; +} + +slist *addptxt(slist *sl, char **s){ + slist *p; + + if(s == NULL) + return sl; + + p = xmalloc(sizeof *p); + p->type = 3; + p->slst = sl; + p->data.ptxt = s; + + return p; +} + +slist *addval(slist *sl, int val){ + slist *p; + + p = xmalloc(sizeof(slist)); + p->type = 2; + p->slst = sl; + p->data.val = val; + + return p; +} + +slist *addsl(slist *sl, slist *sl2){ + slist *p; + if(sl2 == NULL) return sl; + p = xmalloc(sizeof(slist)); + p->type = 0; + p->slst = sl; + p->data.sl = sl2; + return p; +} + +slist *addvec(slist *sl, char *s){ + sl=addval(sl,strlen(s)); + sl=addtxt(sl,"'b "); + sl=addtxt(sl,s); + return sl; +} + +slist *addind(slist *sl){ + if(sl) + sl=addsl(indents[indent],sl); + return sl; +} + +slist *addpar(slist *sl, vrange *v){ + if(v->nlo != NULL) { /* indexes are simple expressions */ + sl=addtxt(sl," ["); + if(v->nhi != NULL){ + sl=addsl(sl,v->nhi); + sl=addtxt(sl,":"); + } + sl=addsl(sl,v->nlo); + sl=addtxt(sl,"] "); + } else { + sl=addtxt(sl," "); + } + return sl; +} + +slist *addpar_snug(slist *sl, vrange *v){ + if(v->nlo != NULL) { /* indexes are simple expressions */ + sl=addtxt(sl,"["); + if(v->nhi != NULL){ + sl=addsl(sl,v->nhi); + sl=addtxt(sl,":"); + } + sl=addsl(sl,v->nlo); + sl=addtxt(sl,"]"); + } + return sl; +} + +slist *addwrap(char *l,slist *sl,char *r){ +slist *s; + s=addtxt(NULL,l); + s=addsl(s,sl); + return addtxt(s,r); +} + +slist *addrem(slist *sl, slist *rem) +{ + if (rem) { + sl=addtxt(sl, " "); + sl=addsl(sl, rem); + } else { + sl=addtxt(sl, "\n"); + } + return sl; +} + +sglist *lookup(sglist *sg,char *s){ + for(;;){ + if(sg == NULL || strcmp(sg->name,s)==0) + return sg; + sg=sg->next; + } +} + +char *sbottom(slist *sl){ + while(sl->slst != NULL) + sl=sl->slst; + return sl->data.txt; +} + +char *inout_string(int type) +{ + char *name=NULL; + switch(type) { + case 0: name="input" ; break; + case 1: name="output" ; break; + case 2: name="inout" ; break; + default: break; + } + return name; +} + +int prec(char op){ + switch(op){ + case 'o': /* others */ + return 9; + break; + case 't':case 'n': + return 8; + break; + case '~': + return 7; + break; + case 'p': case 'm': + return 6; + break; + case '*': case '/': case '%': + return 5; + break; + case '+': case '-': + return 4; + break; + case '&': + return 3; + break; + case '^': + return 2; + break; + case '|': + return 1; + break; + default: + return 0; + break; + } +} + +expdata *addexpr(expdata *expr1,char op,char* opstr,expdata *expr2){ +slist *sl1,*sl2; + if(expr1 == NULL) + sl1=NULL; + else if(expr1->op == 'c') + sl1=addwrap("{",expr1->sl,"}"); + else if(prec(expr1->op) < prec(op)) + sl1=addwrap("(",expr1->sl,")"); + else + sl1=expr1->sl; + + if(expr2->op == 'c') + sl2=addwrap("{",expr2->sl,"}"); + else if(prec(expr2->op) < prec(op)) + sl2=addwrap("(",expr2->sl,")"); + else + sl2=expr2->sl; + + if(expr1 == NULL) + expr1=expr2; + else + free(expr2); + + expr1->op=op; + sl1=addtxt(sl1,opstr); + sl1=addsl(sl1,sl2); + expr1->sl=sl1; + return expr1; +} + +void slTxtReplace(slist *sl, char *match, char *replace){ + if(sl){ + slTxtReplace(sl->slst, match, replace); + switch(sl->type) { + case 0 : + slTxtReplace(sl->data.sl, match, replace); + break; + case 1 : + if (strcmp(sl->data.txt, match) == 0) { + sl->data.txt = replace; + } + break; + case 3 : + if (strcmp(*(sl->data.ptxt), match) == 0) { + *(sl->data.ptxt) = replace; + } + break; + } + } +} + +/* XXX maybe it's a bug that some uses don't munge clocks? */ +slist *add_always(slist *sl, slist *sensitivities, slist *decls, int munge) +{ + int clkedge; + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"always @("); + if (munge) { + clkedge = clkedges[--clkptr]; + if(clkedge) { + sl=addtxt(sl,"posedge "); + /* traverse $4->sl replacing " or " with " or posedge " if there is a clockedge */ + slTxtReplace(sensitivities," or ", " or posedge "); + } else { + sl=addtxt(sl,"negedge "); + slTxtReplace(sensitivities," or ", " or negedge "); + } + } + sl=addsl(sl,sensitivities); + sl=addtxt(sl,") begin"); + if(decls){ + sl=addtxt(sl," : P"); + sl=addval(sl,np++); + sl=addtxt(sl,"\n"); + sl=addsl(sl,decls); + } + sl=addtxt(sl,"\n"); + return sl; +} + +void fixothers(slist *size_expr, slist *sl) { + if(sl) { + fixothers(size_expr, sl->slst); + switch(sl->type) { + case 0 : + fixothers(size_expr,sl->data.sl); + break; + case 4 : { + /* found an (OTHERS => 'x') clause - change to type 0, and insert the + * size_expr for the corresponding signal */ + slist *p; + slist *size_copy = xmalloc(sizeof(slist)); + size_copy = copysl(size_expr); + p = addtxt(NULL, "1'b"); + p = addtxt(p, sl->data.txt); + p = addwrap("{",p,"}"); + p = addsl(size_copy, p); + p = addwrap("{",p,"}"); + sl->type=0; + sl->slst=p; + sl->data.sl=NULL; + break; + } /* case 4 */ + } /* switch */ + } +} + +void findothers(slval *sgin,slist *sl){ + sglist *sg = NULL; + int size = -1; + int useExpr=0; + if(sgin->val>0) { + size=sgin->val; + } else if (sgin->range != NULL) { + if (sgin->range->vtype != tVRANGE) { + size=1; + } else if (sgin->range->sizeval > 0) { + size=sgin->range->sizeval; + } else if (sgin->range->size_expr != NULL) { + useExpr = 1; + fixothers(sgin->range->size_expr, sl); + } + } else { + if((sg=lookup(io_list,sgin->sl->data.txt))==NULL) { + sg=lookup(sig_list,sgin->sl->data.txt); + } + if(sg) { + if(sg->range->vtype != tVRANGE) { + size=1; + } else { + if (sg->range->sizeval > 0) { + size = sg->range->sizeval; + } else { + assert (sg->range->size_expr != NULL); + useExpr = 1; + fixothers(sg->range->size_expr, sl); + } + } + } else { + /* lookup failed, there was no vrange or size value in sgin - so just punt, and assign size=1 */ + size=1; + } /* if(sg) */ + } + if (!useExpr) { + assert(size>0); + /* use size */ + slist *p; + p = addval(NULL,size); + fixothers(p,sl); + } +} + +/* code to find bit number of the msb of n */ +int find_msb(int n) +{ + int k=0; + if(n&0xff00){ + k|=8; + n&=0xff00; + } + if(n&0xf0f0){ + k|=4; + n&=0xf0f0; + } + if(n&0xcccc){ + k|=2; + n&=0xcccc; + } + if(n&0xaaaa){ + k|=1; + n&=0xaaaa; + } + return k; +} + +static char time_unit[2]="\0\0", new_unit[2]="\0\0"; +static void set_timescale(const char *s) +{ + if (0) fprintf(stderr,"set_timescale (%s)\n", s); + new_unit[0] = time_unit[0]; + if (strcasecmp(s,"ms") == 0) { new_unit[0] = 'm'; } + else if (strcasecmp(s,"us") == 0) { new_unit[0] = 'u'; } + else if (strcasecmp(s,"ns") == 0) { new_unit[0] = 'n'; } + else if (strcasecmp(s,"ps") == 0) { new_unit[0] = 'p'; } + else { + fprintf(stderr,"Warning on line %d: AFTER NATURAL NAME pattern" + " matched, but NAME='%s' should be a time unit.\n",lineno,s); + } + if (new_unit[0] != time_unit[0]) { + if (time_unit[0] != 0) { + fprintf(stderr,"Warning on line %d: inconsistent time unit (%s) ignored\n", lineno, s); + } else { + time_unit[0] = new_unit[0]; + } + } +} + +slist *output_timescale(slist *sl) +{ + if (time_unit[0] != 0) { + sl = addtxt(sl, "`timescale 1 "); + sl = addtxt(sl, time_unit); + sl = addtxt(sl, "s / 1 "); + sl = addtxt(sl, time_unit); + sl = addtxt(sl, "s\n"); + } else { + sl = addtxt(sl, "// no timescale needed\n"); + } + return sl; +} + +%} + +%union { + char * txt; /* String */ + int n; /* Value */ + vrange *v; /* Signal range */ + sglist *sg; /* Signal list */ + slist *sl; /* String list */ + expdata *e; /* Expression structure */ + slval *ss; /* Signal structure */ +} + +%token <txt> REM ENTITY IS PORT GENERIC IN OUT INOUT MAP +%token <txt> INTEGER BIT BITVECT DOWNTO TO TYPE END +%token <txt> ARCHITECTURE COMPONENT OF +%token <txt> SIGNAL BEGN NOT WHEN WITH EXIT +%token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT +%token <txt> IF THEN ELSIF ELSE CASE +%token <txt> FOR LOOP GENERATE +%token <txt> AFTER AND OR XOR MOD +%token <txt> LASTVALUE EVENT POSEDGE NEGEDGE +%token <txt> STRING NAME RANGE NULLV +%token <txt> CONVFUNC_2 BASED +%token <n> NATURAL + +%type <n> trad +%type <sl> rem remlist entity +%type <sl> portlist genlist architecture +%type <sl> a_decl a_body p_decl oname +%type <sl> map_list map_item sigvalue +%type <sl> generic_map_list generic_map_item +%type <sl> conf exprc sign_list p_body optname +%type <sl> edge +%type <sl> elsepart wlist wvalue cases +%type <sl> with_item with_list +%type <sg> s_list +%type <n> dir delay +%type <v> type vec_range +%type <n> updown +%type <e> expr +%type <e> simple_expr +%type <ss> signal +%type <txt> opt_is opt_generic opt_entity opt_architecture + +%right '=' +/* Logic operators: */ +%left ORL +%left ANDL +/* Binary operators: */ +%left OR +%left XOR +%left XNOR +%left AND +%left MOD +/* Comparison: */ +%left '<' '>' BIGEQ LESSEQ NOTEQ EQUAL +%left '+' '-' '&' +%left '*' '/' +%right UMINUS UPLUS NOTL NOT + +%error-verbose + +/* rule for "...ELSE IF edge THEN..." causes 1 shift/reduce conflict */ +%expect 1 + +/* glr-parser is needed because processes can start with if statements, but + * not have edges in them - more than one level of look-ahead is needed in that case + * %glr-parser + * unfortunately using glr-parser causes slists to become self-referential, causing core dumps! + */ +%% + +/* Input file must contain entity declaration followed by architecture */ +trad : rem entity rem architecture rem { + slist *sl; + sl=output_timescale($1); + sl=addsl(sl,$2); + sl=addsl(sl,$3); + sl=addsl(sl,$4); + sl=addsl(sl,$5); + sl=addtxt(sl,"\nendmodule\n"); + slprint(sl); + $$=0; + } +/* some people put entity declarations and architectures in separate files - + * translate each piece - note that this will not make a legal Verilog file + * - let them take care of that manually + */ + | rem entity rem { + slist *sl; + sl=addsl($1,$2); + sl=addsl(sl,$3); + sl=addtxt(sl,"\nendmodule\n"); + slprint(sl); + $$=0; + } + | rem architecture rem { + slist *sl; + sl=addsl($1,$2); + sl=addsl(sl,$3); + sl=addtxt(sl,"\nendmodule\n"); + slprint(sl); + $$=0; + } + ; + +/* Comments */ +rem : /* Empty */ {$$=NULL; } + | remlist {$$=$1; } + ; + +remlist : REM {$$=addtxt(indents[indent],$1);} + | REM remlist { + slist *sl; + sl=addtxt(indents[indent],$1); + $$=addsl(sl,$2);} + ; + +opt_is : /* Empty */ {$$=NULL;} | IS ; + +opt_entity : /* Empty */ {$$=NULL;} | ENTITY ; + +opt_architecture : /* Empty */ {$$=NULL;} | ARCHITECTURE ; + +/* tell the lexer to discard or keep comments ('-- ') - this makes the grammar much easier */ +norem : /*Empty*/ {skipRem = 1;} +yesrem : /*Empty*/ {skipRem = 0;} + +/* Entity */ +/* 1 2 3 4 5 6 7 8 9 10 11 12 13 */ +entity : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END opt_entity oname ';' { + slist *sl; + sglist *p; + sl=addtxt(NULL,"\nmodule "); + sl=addtxt(sl,$2); /* NAME */ + sl=addtxt(sl,"(\n"); + /* Add the signal list */ + p=io_list; + for(;;){ + sl=addtxt(sl,p->name); + p=p->next; + if(p) + sl=addtxt(sl,",\n"); + else{ + sl=addtxt(sl,"\n"); + break; + } + } + sl=addtxt(sl,");\n\n"); + sl=addsl(sl,$6); /* rem */ + sl=addsl(sl,$7); /* portlist */ + sl=addtxt(sl,"\n"); + p=io_list; + do{ + sl=addptxt(sl,&(p->type)); + /*sl=addtxt(sl,p->type);*/ + sl=addpar(sl,p->range); + sl=addtxt(sl,p->name); + sl=addtxt(sl,";\n"); + p=p->next; + } while(p!=NULL); + sl=addtxt(sl,"\n"); + sl=addsl(sl,$10); /* rem2 */ + $$=addtxt(sl,"\n"); + } + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 */ + | ENTITY NAME IS GENERIC yeslist '(' rem genlist ')' ';' rem PORT yeslist '(' rem portlist ')' ';' rem END opt_entity oname ';' { + slist *sl; + sglist *p; + if (0) fprintf(stderr,"matched ENTITY GENERIC\n"); + sl=addtxt(NULL,"\nmodule "); + sl=addtxt(sl,$2); /* NAME */ + sl=addtxt(sl,"(\n"); + /* Add the signal list */ + p=io_list; + for(;;){ + sl=addtxt(sl,p->name); + p=p->next; + if(p) + sl=addtxt(sl,",\n"); + else{ + sl=addtxt(sl,"\n"); + break; + } + } + sl=addtxt(sl,");\n\n"); + sl=addsl(sl,$7); /* rem */ + sl=addsl(sl,$8); /* genlist */ + sl=addsl(sl,$11); /* rem */ + sl=addsl(sl,$15); /* rem */ + sl=addsl(sl,$16); /* portlist */ + sl=addtxt(sl,"\n"); + p=io_list; + do{ + sl=addptxt(sl,&(p->type)); + /*sl=addtxt(sl,p->type);*/ + sl=addpar(sl,p->range); + sl=addtxt(sl,p->name); + sl=addtxt(sl,";\n"); + p=p->next; + } while(p!=NULL); + sl=addtxt(sl,"\n"); + sl=addsl(sl,$19); /* rem2 */ + $$=addtxt(sl,"\n"); + } + ; + + /* 1 2 3 4 5 6 7 */ +genlist : s_list ':' type ':' '=' expr rem { + if(dolist){ + slist *sl; + sglist *p; + sl=addtxt(NULL,"parameter"); + sl=addpar(sl,$3); /* type */ + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + sl=addtxt(sl,"="); + sl=addsl(sl, $6->sl); /* expr */ + sl=addtxt(sl,";\n"); + p=p->next; + if(p==NULL) break; + } + $$=addsl(sl,$7); /* rem */ + } else { + $$=NULL; + } + } + /* 1 2 3 4 5 6 7 8 9 */ + | s_list ':' type ':' '=' expr ';' rem genlist { + if(dolist){ + slist *sl; + sglist *p; + sl=addtxt(NULL,"parameter"); + sl=addpar(sl,$3); /* type */ + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + sl=addtxt(sl,"="); + sl=addsl(sl, $6->sl); /* expr */ + sl=addtxt(sl,";\n"); + p=p->next; + if(p==NULL) break; + } + $$=addsl(sl,$8); /* rem */ + $$=addsl(sl,$9); /* genlist */ + } else { + $$=NULL; + } + } + /* 1 2 3 4 5 6 */ + | s_list ':' type ';' rem genlist { + if(dolist){ + slist *sl; + sglist *p; + sl=addtxt(NULL,"parameter"); + sl=addpar(sl,$3); /* type */ + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + sl=addtxt(sl,";\n"); + p=p->next; + if(p==NULL) break; + } + $$=addsl(sl,$5); /* rem */ + $$=addsl(sl,$6); /* genlist */ + } else { + $$=NULL; + } + } + /* 1 2 3 4 */ + | s_list ':' type rem { + if(dolist){ + slist *sl; + sglist *p; + sl=addtxt(NULL,"parameter"); + sl=addpar(sl,$3); /* type */ + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + sl=addtxt(sl,";\n"); + p=p->next; + if(p==NULL) break; + } + $$=addsl(sl,$4); /* rem */ + } else { + $$=NULL; + } + } + ; + + /* 1 2 3 4 5 */ +portlist : s_list ':' dir type rem { + slist *sl; + sglist *p; + + if(dolist){ + sl=addtxt(NULL,inout_string($3)); + sl=addpar(sl,$4); + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + p=p->next; + if(p==NULL) + break; + sl=addtxt(sl,", "); + } + sl=addtxt(sl,";\n"); + $$=addsl(sl,$5); + io_list=p=$1; + for(;;){ + p->type=wire; + p->range=$4; + if(p->next==NULL) + break; + p=p->next; + } + } else{ + free($5); + free($4); + } + } + | s_list ':' dir type ';' rem portlist { + slist *sl; + sglist *p; + + if(dolist){ + sl=addtxt(NULL,inout_string($3)); + sl=addpar(sl,$4); + p=$1; + for(;;){ + sl=addtxt(sl,p->name); + p=p->next; + if(p==NULL) + break; + sl=addtxt(sl,", "); + } + sl=addtxt(sl,";\n"); + sl=addsl(sl,$6); + $$=addsl(sl,$7); + p=$1; + for(;;){ + p->type=wire; + p->range=$4; + if(p->next==NULL) + break; + p=p->next; + } + p->next=io_list; + io_list=$1; + } else{ + free($6); + free($4); + } + } + ; + +dir : IN { $$=0;} + | OUT { $$=1; } + | INOUT { $$=2; } + ; + +type : BIT { + $$=xmalloc(sizeof(vrange)); + $$->vtype =tSCALAR; + $$->nlo = NULL; + $$->nhi = NULL; + } + | INTEGER { + $$=xmalloc(sizeof(vrange)); + $$->vtype =tSCALAR; + $$->nlo = addtxt(NULL,"0"); + $$->nhi = addtxt(NULL,"31"); + } + | BITVECT '(' vec_range ')' {$$=$3;} + | NAME { + sglist *sg; + + sg=lookup(type_list,$1); + if(sg) + $$=sg->range; + else{ + fprintf(stderr,"Undefined type '%s' on line %d\n",$1,lineno); + YYABORT; + } + } + ; + +/* using expr instead of simple_expr here makes the grammar ambiguous (why?) */ +vec_range : simple_expr updown simple_expr { + $$=xmalloc(sizeof(vrange)); + $$->vtype=tVRANGE; + $$->nhi=$1->sl; + $$->nlo=$3->sl; + $$->size_expr = NULL; + $$->sizeval = -1; /* undefined size */ + /* calculate the width of this vrange */ + if ($1->op == 'n' && $3->op == 'n') { + if ($2==-1) { /* (nhi:natural downto nlo:natural) */ + $$->sizeval = $1->value - $3->value + 1; + } else { /* (nhi:natural to nlo:natural) */ + $$->sizeval = $3->value - $1->value + 1; + } + } else { + /* make an expression to calculate the width of this vrange: + * create an expression that calculates: + * size expr = (simple_expr1) - (simple_expr2) + 1 + */ + expdata *size_expr1 = xmalloc(sizeof(expdata)); + expdata *size_expr2 = xmalloc(sizeof(expdata)); + expdata *diff12 = xmalloc(sizeof(expdata)); + expdata *plusone = xmalloc(sizeof(expdata)); + expdata *finalexpr = xmalloc(sizeof(expdata)); + size_expr1->sl = addwrap("(",$1->sl,")"); + size_expr2->sl = addwrap("(",$3->sl,")"); + plusone->op='t'; + plusone->sl=addtxt(NULL,"1"); + if ($2==-1) { + /* (simple_expr1 downto simple_expr1) */ + diff12 = addexpr(size_expr1,'-',"-",size_expr2); + } else { + /* (simple_expr1 to simple_expr1) */ + diff12 = addexpr(size_expr2,'-',"-",size_expr1); + } + finalexpr = addexpr(diff12,'+',"+",plusone); + finalexpr->sl = addwrap("(",finalexpr->sl,")"); + $$->size_expr = finalexpr->sl; + } + } + | simple_expr { + $$=xmalloc(sizeof(vrange)); + $$->vtype=tSUBSCRIPT; + $$->nhi=NULL; + $$->nlo=$1->sl; + } + | NAME '\'' RANGE { + /* lookup NAME and copy its vrange */ + $$=xmalloc(sizeof(vrange)); + sglist *sg = NULL; + if((sg=lookup(io_list,$1))==NULL) { + sg=lookup(sig_list,$1); + } + if(sg) { + $$ = sg->range; + } else { + fprintf(stderr,"Undefined range \"%s'range\" on line %d\n",$1,lineno); + YYABORT; + } + } + ; + +updown : DOWNTO {$$=-1} + | TO {$$=1} + ; + +/* Architecture */ +architecture : ARCHITECTURE NAME OF NAME IS rem a_decl + BEGN doindent a_body END opt_architecture oname ';' unindent { + slist *sl; + sl=addsl($6,$7); + sl=addtxt(sl,"\n"); + $$=addsl(sl,$10); + } + ; + +/* Extends indentation by one level */ +doindent : /* Empty */ {indent= indent < MAXINDENT ? indent + 1 : indent;} + ; +/* Shorten indentation by one level */ +unindent : /* Empty */ {indent= indent > 0 ? indent - 1 : indent;} + +/* Declarative part of the architecture */ +a_decl : {$$=NULL;} + | a_decl SIGNAL s_list ':' type ';' rem { + sglist *sg; + slist *sl; + int size; + + if($5->vtype==tSUBSCRIPT) + size=1; + else + size=-1; + sl=$1; + sg=$3; + for(;;){ + sg->type=wire; + sg->range=$5; + sl=addptxt(sl,&(sg->type)); + sl=addpar(sl,$5); + sl=addtxt(sl,sg->name); + sl=addtxt(sl,";"); + if(sg->next == NULL) + break; + sl=addtxt(sl," "); + sg=sg->next; + } + sg->next=sig_list; + sig_list=$3; + $$=addrem(sl,$7); + } + | a_decl CONSTANT NAME ':' type ':' '=' expr ';' rem { + slist * sl; + sl=addtxt($1,"parameter "); + sl=addtxt(sl,$3); + sl=addtxt(sl," = "); + sl=addsl(sl,$8->sl); + sl=addtxt(sl,";"); + $$=addrem(sl,$10); + } + | a_decl TYPE NAME IS '(' s_list ')' ';' rem { + slist *sl, *sl2; + sglist *p; + int n,k; + n=0; + sl=NULL; + p=$6; + for(;;){ + sl=addtxt(sl," "); + sl=addtxt(sl,p->name); + sl=addtxt(sl," = "); + sl=addval(sl,n++); + p=p->next; + if(p==NULL){ + sl=addtxt(sl,";\n"); + break; + } else + sl=addtxt(sl,",\n"); + } + n--; + k=find_msb(n); + sl2=addtxt(NULL,"parameter ["); + sl2=addval(sl2,k); + sl2=addtxt(sl2,":0]\n"); + sl=addsl(sl2,sl); + sl=addsl($1,sl); + $$=addrem(sl,$9); + p=xmalloc(sizeof(sglist)); + p->name=$3; + p->range=xmalloc(sizeof(vrange)); + if(k>0) { + p->range->vtype = tVRANGE; + p->range->sizeval = k+1; + p->range->nhi=addval(NULL,k); + p->range->nlo=addtxt(NULL,"0"); + } else { + p->range->vtype = tSCALAR; + p->range->nhi= NULL; + p->range->nlo= NULL; + } + p->next=type_list; + type_list=p; + } +/* 1 2 3 4 5r1 6 7 8 9r2 10 11 12 13r3 14 15 16 17 18 19r4 */ + | a_decl COMPONENT NAME opt_is rem opt_generic PORT nolist '(' rem portlist ')' ';' rem END COMPONENT oname ';' yeslist rem { + $$=addsl($1,$20); /* a_decl, rem4 */ + free($3); /* NAME */ + free($10); /* rem2 */ + free($14);/* rem3 */ + } + ; + +opt_generic : /* Empty */ {$$=NULL;} + | GENERIC nolist '(' rem genlist ')' ';' rem { + if (0) fprintf(stderr,"matched opt_generic\n"); + free($4); /* rem */ + free($8); /* rem */ + $$=NULL; + } + ; + +nolist : /*Empty*/ {dolist = 0;} +yeslist : /*Empty*/ {dolist = 1;} + +/* XXX wishlist: record comments into slist, play them back later */ +s_list : NAME rem { + sglist * sg; + if(dolist){ + sg=xmalloc(sizeof(sglist)); + sg->name=$1; + sg->next=NULL; + $$=sg; + } else{ + free($1); + $$=NULL; + } + free($2); + } + | NAME ',' rem s_list { + sglist * sg; + if(dolist){ + sg=xmalloc(sizeof(sglist)); + sg->name=$1; + sg->next=$4; + $$=sg; + } else{ + free($1); + $$=NULL; + } + free($3); + } + ; + +a_body : rem {$$=addind($1);} + /* 1 2 3 4 5 6 7 8 9 */ + | rem signal '<' '=' rem norem sigvalue yesrem a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"assign "); + sl=addsl(sl,$2->sl); + findothers($2,$7); + free($2); + sl=addtxt(sl," = "); + sl=addsl(sl,$7); + sl=addtxt(sl,";\n"); + $$=addsl(sl,$9); + } + /* 1 2 3 4 5 6 7 8 9 10 11 */ + | rem WITH expr SELECT rem yeswith signal '<' '=' with_list a_body { + slist *sl; + sglist *sg; + char *s; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"always @(*) begin\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," case("); + sl=addsl(sl,$3->sl); + free($3); + sl=addtxt(sl,")\n"); + if($5) + sl=addsl(sl,$5); + s=sbottom($7->sl); + if((sg=lookup(io_list,s))==NULL) + sg=lookup(sig_list,s); + if(sg) + sg->type=reg; + findothers($7,$10); + free($7); + sl=addsl(sl,$10); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," endcase\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n\n"); + $$=addsl(sl,$11); + } + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 */ + | rem NAME ':' NAME PORT MAP '(' doindent map_list rem ')' ';' unindent a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,$4); /* NAME2 */ + sl=addtxt(sl," "); + sl=addtxt(sl,$2); /* NAME1 */ + sl=addtxt(sl,"(\n"); + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$9); /* map_list */ + sl=addtxt(sl,");\n\n"); + $$=addsl(sl,$14); /* a_body */ + } + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 */ + | rem NAME ':' NAME GENERIC MAP '(' doindent generic_map_list ')' unindent PORT MAP '(' doindent map_list ')' ';' unindent a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,$4); /* NAME2 (component name) */ + sl=addtxt(sl," #(\n"); + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$9); /* (generic) map_list */ + sl=addtxt(sl,")\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,$2); /* NAME1 (instance name) */ + sl=addtxt(sl,"(\n"); + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$16); /* map_list */ + sl=addtxt(sl,");\n\n"); + $$=addsl(sl,$20); /* a_body */ + } + | optname PROCESS '(' sign_list ')' p_decl opt_is BEGN doindent p_body END PROCESS oname ';' unindent a_body { + slist *sl; + if (0) fprintf(stderr,"process style 1\n"); + sl=add_always($1,$4,$6,0); + sl=addsl(sl,$10); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n\n"); + $$=addsl(sl,$16); + } + | optname PROCESS '(' sign_list ')' p_decl opt_is BEGN doindent + rem IF edge THEN p_body END IF ';' END PROCESS oname ';' unindent a_body { + slist *sl; + if (0) fprintf(stderr,"process style 2: if then end if\n"); + sl=add_always($1,$4,$6,1); + if($10){ + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$10); + } + sl=addsl(sl,$14); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n\n"); + $$=addsl(sl,$23); + } + /* 1 2 3 4 5 6 7 8 9 */ + | optname PROCESS '(' sign_list ')' p_decl opt_is BEGN doindent + /* 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 */ + rem IF exprc THEN doindent p_body unindent ELSIF edge THEN doindent p_body unindent END IF ';' + /* 26 27 28 29 30 31 */ + END PROCESS oname ';' unindent a_body { + slist *sl; + if (0) fprintf(stderr,"process style 3: if then elsif then end if\n"); + sl=add_always($1,$4,$6,1); + if($10){ + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$10); + } + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," if("); + sl=addsl(sl,$12); + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,$15); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," end else begin\n"); + sl=addsl(sl,$21); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," end\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n\n"); + $$=addsl(sl,$31); + } + /* 1 2 3 4 5 6 7 8 9 */ + | optname PROCESS '(' sign_list ')' p_decl opt_is BEGN doindent + /* 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 */ + rem IF exprc THEN doindent p_body unindent ELSE IF edge THEN doindent p_body unindent END IF ';' END IF ';' + /* 30 31 32 33 34 35 */ + END PROCESS oname ';' unindent a_body { + slist *sl; + if (0) fprintf(stderr,"process style 4: if then else if then end if\n"); + sl=add_always($1,$4,$6,1); + if($10){ + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$10); + } + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," if("); + sl=addsl(sl,$12); /* exprc */ + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,$15); /* p_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," end else begin\n"); + sl=addsl(sl,$22); /* p_body:2 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl," end\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n\n"); + $$=addsl(sl,$35); /* a_body */ + } + + /* note vhdl does not allow an else in an if generate statement */ + /* 1 2 3 4 5 6 7 8 9 10 11 12 */ + | optname IF exprc GENERATE doindent a_body unindent END GENERATE oname ';' a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"generate "); + sl=addtxt(sl,"if ("); + sl=addsl(sl,$3); /* exprc */ + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$6); /* a_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"endgenerate\n"); + $$=addsl(sl,$12); /* a_body:2 */ + } + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */ + | optname FOR signal IN expr TO expr GENERATE doindent a_body unindent END GENERATE oname ';' a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"genvar "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,";\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"generate "); + sl=addtxt(sl,"for ("); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,"="); + sl=addsl(sl,$5->sl); /* expr:1 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," <= "); + sl=addsl(sl,$7->sl); /* expr:2 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," = "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," + 1) begin\n"); + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$10); /* a_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"endgenerate\n"); + $$=addsl(sl,$16); /* a_body:2 */ + } + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */ + | optname FOR signal IN expr DOWNTO expr GENERATE doindent a_body unindent END GENERATE oname ';' a_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"generate "); + sl=addtxt(sl,"for ("); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,"="); + sl=addsl(sl,$5->sl); /* expr:1 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," >= "); + sl=addsl(sl,$7->sl); /* expr:2 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," = "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," - 1) begin\n"); + sl=addsl(sl,$10); /* a_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"endgenerate\n"); + $$=addsl(sl,$16); /* a_body:2 */ + } + ; + +oname : {$$=NULL;} + | NAME {free($1); $$=NULL;} + ; + +optname : rem {$$=$1;} + | rem NAME ':' {$$=$1; free($2);} + ; + +edge : '(' edge ')' {$$=addwrap("(",$2,")");} + | NAME '\'' EVENT AND exprc { + clkedges[clkptr++]=$5->data.sl->data.txt[0]-'0'; + assert(clkptr < MAXEDGES); + } + | exprc AND NAME '\'' EVENT { + clkedges[clkptr++]=$1->data.sl->data.txt[0]-'0'; + clkptr++; + assert(clkptr < MAXEDGES); + } + | POSEDGE '(' NAME ')' { + clkedges[clkptr++]=1; + assert(clkptr < MAXEDGES); + } + | NEGEDGE '(' NAME ')' { + clkedges[clkptr++]=0; + assert(clkptr < MAXEDGES); + } + ; + +yeswith : {dowith=1;} + +with_list : with_item ';' {$$=$1;} + | with_item ',' rem with_list { + slist *sl; + if($3){ + sl=addsl($1,$3); + $$=addsl(sl,$4); + } else + $$=addsl($1,$4); + } + | expr delay WHEN OTHERS ';' { + slist *sl; + sl=addtxt(indents[indent]," default : "); + sl=addsl(sl,slwith); + sl=addtxt(sl," <= "); + if(delay && $2){ + sl=addtxt(sl,"# "); + sl=addval(sl,$2); + sl=addtxt(sl," "); + } + if($1->op == 'c') + sl=addsl(sl,addwrap("{",$1->sl,"}")); + else + sl=addsl(sl,$1->sl); + free($1); + delay=1; + $$=addtxt(sl,";\n"); + } + +with_item : expr delay WHEN wlist { + slist *sl; + sl=addtxt(indents[indent]," "); + sl=addsl(sl,$4); + sl=addtxt(sl," : "); + sl=addsl(sl,slwith); + sl=addtxt(sl," <= "); + if(delay && $2){ + sl=addtxt(sl,"# "); + sl=addval(sl,$2); + sl=addtxt(sl," "); + } + if($1->op == 'c') + sl=addsl(sl,addwrap("{",$1->sl,"}")); + else + sl=addsl(sl,$1->sl); + free($1); + delay=1; + $$=addtxt(sl,";\n"); + } + +p_decl : rem {$$=$1} + | rem VARIABLE s_list ':' type ';' p_decl { + slist *sl; + sglist *sg, *p; + sl=addtxt($1," reg"); + sl=addpar(sl,$5); + free($5); + sg=$3; + for(;;){ + sl=addtxt(sl,sg->name); + p=sg; + sg=sg->next; + free(p); + if(sg) + sl=addtxt(sl,", "); + else + break; + } + sl=addtxt(sl,";\n"); + $$=addsl(sl,$7); + } + | rem VARIABLE s_list ':' type ':' '=' expr ';' p_decl { + slist *sl; + sglist *sg, *p; + sl=addtxt($1," reg"); + sl=addpar(sl,$5); + free($5); + sg=$3; + for(;;){ + sl=addtxt(sl,sg->name); + p=sg; + sg=sg->next; + free(p); + if(sg) + sl=addtxt(sl,", "); + else + break; + } + sl=addtxt(sl," = "); + sl=addsl(sl,$8->sl); + sl=addtxt(sl,";\n"); + $$=addsl(sl,$10); + } + ; + +p_body : rem {$$=$1;} + /* 1 2 3 4 5 6 7 8 9 */ + | rem signal ':' '=' norem expr ';' yesrem p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addsl(sl,$2->sl); + findothers($2,$6->sl); + sl=addtxt(sl," = "); + if($6->op == 'c') + sl=addsl(sl,addwrap("{",$6->sl,"}")); + else + sl=addsl(sl,$6->sl); + sl=addtxt(sl,";\n"); + $$=addsl(sl,$9); + } + /* 1 2 3 4 5 6 7 8 */ + | rem signal norem '<' '=' sigvalue yesrem p_body { + slist *sl; + sglist *sg; + char *s; + + s=sbottom($2->sl); + if((sg=lookup(io_list,s))==NULL) + sg=lookup(sig_list,s); + if(sg) + sg->type=reg; + sl=addsl($1,indents[indent]); + sl=addsl(sl,$2->sl); + findothers($2,$6); + sl=addtxt(sl," <= "); + sl=addsl(sl,$6); + sl=addtxt(sl,";\n"); + $$=addsl(sl,$8); + } +/* 1 2 3 4 5 6:1 7 8 9 10 11 12:2 */ + | rem IF exprc THEN doindent p_body unindent elsepart END IF ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"if("); + sl=addsl(sl,$3); + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,$6); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + sl=addsl(sl,$8); + $$=addsl(sl,$12); + } +/* 1 2 3 4 5:1 6 7:2 8 9 10:1 11 12 13 14 15:2 */ + | rem FOR signal IN expr TO expr LOOP doindent p_body unindent END LOOP ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"for ("); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,"="); + sl=addsl(sl,$5->sl); /* expr:1 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," <= "); + sl=addsl(sl,$7->sl); /* expr:2 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," = "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," + 1) begin \n"); + sl=addsl(sl,$10); /* p_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + $$=addsl(sl,$15); /* p_body:2 */ + } +/* 1 2 3 4 5:1 6 7:2 8 9 10:1 11 12 13 14 15:2 */ + | rem FOR signal IN expr DOWNTO expr LOOP doindent p_body unindent END LOOP ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"for ("); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,"="); + sl=addsl(sl,$5->sl); /* expr:1 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," >= "); + sl=addsl(sl,$7->sl); /* expr:2 */ + sl=addtxt(sl,"; "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," = "); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl," - 1) begin\n"); + sl=addsl(sl,$10); /* p_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + $$=addsl(sl,$15); /* p_body:2 */ + } +/* 1 2 3 4 5 6 7 8 9 10 */ + | rem CASE signal IS rem cases END CASE ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"case("); + sl=addsl(sl,$3->sl); /* signal */ + sl=addtxt(sl,")\n"); + if($5){ + sl=addsl(sl,indents[indent]); + sl=addsl(sl,$5); + } + sl=addsl(sl,$6); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"endcase\n"); + $$=addsl(sl,$10); + } + | rem EXIT ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"disable; //VHD2VL: add block name here\n"); + $$=addsl(sl,$4); + } + | rem NULLV ';' p_body { + slist *sl; + if($1){ + sl=addsl($1,indents[indent]); + $$=addsl(sl,$4); + }else + $$=$4; + } + ; + +elsepart : {$$=NULL;} + | ELSIF exprc THEN doindent p_body unindent elsepart { + slist *sl; + sl=addtxt(indents[indent],"else if("); + sl=addsl(sl,$2); + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,$5); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + $$=addsl(sl,$7); + } + | ELSE doindent p_body unindent { + slist *sl; + sl=addtxt(indents[indent],"else begin\n"); + sl=addsl(sl,$3); + sl=addsl(sl,indents[indent]); + $$=addtxt(sl,"end\n"); + } + ; + +cases : WHEN wlist '=' '>' doindent p_body unindent cases{ + slist *sl; + sl=addsl(indents[indent],$2); + sl=addtxt(sl," : begin\n"); + sl=addsl(sl,$6); + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + $$=addsl(sl,$8); + } + | WHEN OTHERS '=' '>' doindent p_body unindent { + slist *sl; + sl=addtxt(indents[indent],"default : begin\n"); + sl=addsl(sl,$6); + sl=addsl(sl,indents[indent]); + $$=addtxt(sl,"end\n"); + } + | /* Empty */ { $$=NULL; } /* List without WHEN OTHERS */ + ; + +wlist : wvalue {$$=$1;} + | wlist '|' wvalue { + slist *sl; + sl=addtxt($1,","); + $$=addsl(sl,$3); + } + ; + +wvalue : STRING {$$=addvec(NULL,$1);} + | NAME {$$=addtxt(NULL,$1);} + ; + +sign_list : signal {$$=$1->sl; free($1);} + | signal ',' sign_list { + slist *sl; + sl=addtxt($1->sl," or "); + free($1); + $$=addsl(sl,$3); + } + ; + +sigvalue : expr delay ';' { + slist *sl; + if(delay && $2){ + sl=addtxt(NULL,"# "); + sl=addval(sl,$2); + sl=addtxt(sl," "); + } else + sl=NULL; + if($1->op == 'c') + sl=addsl(sl,addwrap("{",$1->sl,"}")); + else + sl=addsl(sl,$1->sl); + free($1); + delay=1; + $$=sl; + } + | expr delay WHEN exprc ';' { + fprintf(stderr,"Warning on line %d: Can't translate 'expr delay WHEN exprc;' expressions\n",lineno); + $$=NULL; + } + | expr delay WHEN exprc ELSE nodelay sigvalue { + slist *sl; + sl=addtxt($4," ? "); + if($1->op == 'c') + sl=addsl(sl,addwrap("{",$1->sl,"}")); + else + sl=addsl(sl,$1->sl); + free($1); + sl=addtxt(sl," : "); + $$=addsl(sl,$7); + } + ; + +nodelay : /* empty */ {delay=0;} + ; + +delay : /* empty */ {$$=0;} + | AFTER NATURAL NAME { + set_timescale($3); + $$=$2; + } + ; + +map_list : rem map_item { + slist *sl; + sl=addsl($1,indents[indent]); + $$=addsl(sl,$2);} + | rem map_item ',' map_list { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addsl(sl,$2); + sl=addtxt(sl,",\n"); + $$=addsl(sl,$4); + } + ; + +map_item : signal {$$=$1->sl; free($1);} + | NAME '=' '>' signal { + slist *sl; + sl=addtxt(NULL,"."); + sl=addtxt(sl,$1); + sl=addtxt(sl,"("); + sl=addsl(sl,$4->sl); + free($4); + $$=addtxt(sl,")"); + } + ; + +generic_map_list : rem generic_map_item { + slist *sl; + sl=addsl($1,indents[indent]); + $$=addsl(sl,$2);} + | rem generic_map_item ',' generic_map_list { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addsl(sl,$2); + sl=addtxt(sl,",\n"); + $$=addsl(sl,$4); + } + ; + +generic_map_item : NAME '=' '>' expr { + slist *sl; + sl=addtxt(NULL,"."); + sl=addtxt(sl,$1); + sl=addtxt(sl,"("); + sl=addsl(sl,$4->sl); + $$=addtxt(sl,")"); + } + ; + +signal : NAME { + slist *sl; + slval *ss; + ss=xmalloc(sizeof(slval)); + sl=addtxt(NULL,$1); + if(dowith){ + slwith=sl; + dowith=0; + } + ss->sl=sl; + ss->val=-1; + ss->range=NULL; + $$=ss; + } + | NAME '(' vec_range ')' { + slval *ss; + slist *sl; + ss=xmalloc(sizeof(slval)); + sl=addtxt(NULL,$1); + sl=addpar_snug(sl,$3); + if(dowith){ + slwith=sl; + dowith=0; + } + ss->sl=sl; + ss->range=$3; + if($3->vtype==tVRANGE) { + ss->val=1; + } else { + ss->val = -1; /* width is in the vrange */ + } + $$=ss; + } + ; + +/* Expressions */ +expr : signal { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='t'; /* Terminal symbol */ + e->sl=$1->sl; + free($1); + $$=e; + } + | STRING { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='t'; /* Terminal symbol */ + e->sl=addvec(NULL,$1); + $$=e; + } + | NATURAL { + expdata *e=xmalloc(sizeof(expdata)); + e->op='t'; /* Terminal symbol */ + e->sl=addval(NULL,$1); + $$=e; + } + | NATURAL BASED { /* e.g. 16#55aa# */ + expdata *e=xmalloc(sizeof(expdata)); + char *natval = xmalloc(strlen($2)+34); + e->op='t'; /* Terminal symbol */ + switch($1) { + case 2: + sprintf(natval, "'B%s",$2); + break; + case 8: + sprintf(natval, "'O%s",$2); + break; + case 10: + sprintf(natval, "'D%s",$2); + break; + case 16: + sprintf(natval, "'H%s",$2); + break; + default: + sprintf(natval,"%d#%s#",$1,$2); + fprintf(stderr,"Warning on line %d: Can't translate based number %s (only bases of 2, 8, 10, and 16 are translatable)\n",lineno,natval); + } + e->sl=addtxt(NULL,natval); + $$=e; + } + | NAME STRING { + expdata *e=xmalloc(sizeof(expdata)); + char *natval = xmalloc(strlen($2)+3); + if (strcasecmp($1,"X") != 0) { + fprintf(stderr,"Warning on line %d: NAME STRING rule matched but NAME='%s' is not X.\n",lineno, $1); + } + e->op='t'; /* Terminal symbol */ + sprintf(natval, "'H%s",$2); + e->sl=addtxt(NULL,natval); + $$=e; + } + | '(' OTHERS '=' '>' STRING ')' { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='o'; /* others */ + e->sl=addothers(NULL,$5); + $$=e; + } + | expr '&' expr { /* Vector chaining */ + slist *sl; + sl=addtxt($1->sl,","); + sl=addsl(sl,$3->sl); + free($3); + $1->op='c'; + $1->sl=sl; + $$=$1; + } + | '-' expr %prec UMINUS {$$=addexpr(NULL,'m'," -",$2);} + | '+' expr %prec UPLUS {$$=addexpr(NULL,'p'," +",$2);} + | expr '+' expr {$$=addexpr($1,'+'," + ",$3);} + | expr '-' expr {$$=addexpr($1,'-'," - ",$3);} + | expr '*' expr {$$=addexpr($1,'*'," * ",$3);} + | expr '/' expr {$$=addexpr($1,'/'," / ",$3);} + | expr MOD expr {$$=addexpr($1,'%'," % ",$3);} + | NOT expr {$$=addexpr(NULL,'~'," ~",$2);} + | expr AND expr {$$=addexpr($1,'&'," & ",$3);} + | expr OR expr {$$=addexpr($1,'|'," | ",$3);} + | expr XOR expr {$$=addexpr($1,'^'," ^ ",$3);} + | expr XNOR expr {$$=addexpr(NULL,'~'," ~",addexpr($1,'^'," ^ ",$3));} + | BITVECT '(' expr ')' { + /* single argument type conversion function e.g. std_ulogic_vector(x) */ + expdata *e; + e=xmalloc(sizeof(expdata)); + if ($3->op == 'c') { + e->sl=addwrap("{",$3->sl,"}"); + } else { + e->sl=addwrap("(",$3->sl,")"); + } + $$=e; + } + | CONVFUNC_2 '(' expr ',' NATURAL ')' { + /* two argument type conversion e.g. to_unsigned(x, 3) */ + expdata *e; + e=xmalloc(sizeof(expdata)); + if ($3->op == 'c') { + e->sl=addwrap("{",$3->sl,"}"); + } else { + e->sl=addwrap("(",$3->sl,")"); + } + $$=e; + } + | CONVFUNC_2 '(' expr ',' NAME ')' { + expdata *e; + e=xmalloc(sizeof(expdata)); + if ($3->op == 'c') { + e->sl=addwrap("{",$3->sl,"}"); + } else { + e->sl=addwrap("(",$3->sl,")"); + } + $$=e; + } + | '(' expr ')' { + expdata *e; + e=xmalloc(sizeof(expdata)); + if ($2->op == 'c') { + e->sl=addwrap("{",$2->sl,"}"); + } else { + e->sl=addwrap("(",$2->sl,")"); + } + $$=e; + } + ; + +/* Conditional expressions */ +exprc : conf { $$=$1; } + | '(' exprc ')' { + $$=addwrap("(",$2,")"); + } + | exprc AND exprc %prec ANDL { + slist *sl; + sl=addtxt($1," && "); + $$=addsl(sl,$3); + } + | exprc OR exprc %prec ORL { + slist *sl; + sl=addtxt($1," || "); + $$=addsl(sl,$3); + } + | NOT exprc %prec NOTL { + slist *sl; + sl=addtxt(NULL,"!"); + $$=addsl(sl,$2); + } + ; + +/* Comparisons */ +conf : expr '=' expr %prec EQUAL { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} == "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") == "); + else + sl=addtxt($1->sl," == "); + if($3->op == 'c') + $$=addsl(sl,addwrap("{",$3->sl,"}")); + else if($3->op != 't') + $$=addsl(sl,addwrap("(",$3->sl,")")); + else + $$=addsl(sl,$3->sl); + free($1); + free($3); + } + | expr '>' expr { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} > "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") > "); + else + sl=addtxt($1->sl," > "); + if($3->op == 'c') + $$=addsl(sl,addwrap("{",$3->sl,"}")); + else if($3->op != 't') + $$=addsl(sl,addwrap("(",$3->sl,")")); + else + $$=addsl(sl,$3->sl); + free($1); + free($3); + } + | expr '>' '=' expr %prec BIGEQ { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} >= "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") >= "); + else + sl=addtxt($1->sl," >= "); + if($4->op == 'c') + $$=addsl(sl,addwrap("{",$4->sl,"}")); + else if($4->op != 't') + $$=addsl(sl,addwrap("(",$4->sl,")")); + else + $$=addsl(sl,$4->sl); + free($1); + free($4); + } + | expr '<' expr { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} < "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") < "); + else + sl=addtxt($1->sl," < "); + if($3->op == 'c') + $$=addsl(sl,addwrap("{",$3->sl,"}")); + else if($3->op != 't') + $$=addsl(sl,addwrap("(",$3->sl,")")); + else + $$=addsl(sl,$3->sl); + free($1); + free($3); + } + | expr '<' '=' expr %prec LESSEQ { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} <= "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") <= "); + else + sl=addtxt($1->sl," <= "); + if($4->op == 'c') + $$=addsl(sl,addwrap("{",$4->sl,"}")); + else if($4->op != 't') + $$=addsl(sl,addwrap("(",$4->sl,")")); + else + $$=addsl(sl,$4->sl); + free($1); + free($4); + } + | expr '/' '=' expr %prec NOTEQ { + slist *sl; + if($1->op == 'c') + sl=addwrap("{",$1->sl,"} != "); + else if($1->op != 't') + sl=addwrap("(",$1->sl,") != "); + else + sl=addtxt($1->sl," != "); + if($4->op == 'c') + $$=addsl(sl,addwrap("{",$4->sl,"}")); + else if($4->op != 't') + $$=addsl(sl,addwrap("(",$4->sl,")")); + else + $$=addsl(sl,$4->sl); + free($1); + free($4); + } + ; + +simple_expr : signal { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='t'; /* Terminal symbol */ + e->sl=$1->sl; + free($1); + $$=e; + } + | STRING { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='t'; /* Terminal symbol */ + e->sl=addvec(NULL,$1); + $$=e; + } + | NATURAL { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->op='n'; /* natural */ + e->value=$1; + e->sl=addval(NULL,$1); + $$=e; + } + | simple_expr '+' simple_expr { + $$=addexpr($1,'+'," + ",$3); + } + | simple_expr '-' simple_expr { + $$=addexpr($1,'-'," - ",$3); + } + | simple_expr '*' simple_expr { + $$=addexpr($1,'*'," * ",$3); + } + | simple_expr '/' simple_expr { + $$=addexpr($1,'/'," / ",$3); + } + | '(' simple_expr ')' { + expdata *e; + e=xmalloc(sizeof(expdata)); + e->sl=addwrap("(",$2->sl,")"); + $$=e; + } + ; + +%% + +char *outfile; /* Output file */ +char *sourcefile; /* Input file */ + +int main(int argc, char *argv[]){ +int i,j; +char *s; +slist *sl; +int status; + + /* Init the indentation variables */ + indents[0]=NULL; + for(i=1;i<MAXINDENT;i++){ + indents[i]=sl=xmalloc(sizeof(slist)); + sl->data.txt=s=xmalloc(sizeof(char) *((i<<1)+1)); + for(j=0;j<(i<<1);j++) + *s++=' '; + *s=0; + sl->type=1; + sl->slst=NULL; + } + + if ((argc>=2) && strcmp(argv[1], "-d") == 0) { + yydebug = 1; + argv++; + argc--; + } + + if (argc>=2) { + sourcefile = argv[1]; + if (strcmp(sourcefile,"-")!=0 && !freopen(sourcefile, "r", stdin)) { + fprintf(stderr, "Error: Can't open input file '%s'\n", sourcefile); + return(1); + } + } else { + sourcefile = "-"; + } + + if (argc>=3) { + outfile = argv[2]; + if (strcmp(outfile,"-")!=0 && !freopen(outfile, "w", stdout)) { + fprintf(stderr, "Error: Can't open output file '%s'\n", outfile); + return(1); + } + } else { + outfile = "-"; + } + + printf("// File %s translated with vhd2vl v2.2 VHDL to Verilog RTL translator\n\n", sourcefile); + fputs( +"// vhd2vl is Free (libre) Software:\n" +"// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd\n" +"// http://www.ocean-logic.com\n" +"// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc\n" +"// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL\n" +"// http://doolittle.icarus.com/~larry/vhd2vl/\n" +"//\n" +"// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting\n" +"// Verilog for correctness, ideally with a formal verification tool.\n" +"//\n" +"// You are welcome to redistribute vhd2vl under certain conditions.\n" +"// See the license (GPLv2) file included with the source for details.\n\n" +"// The result of translation follows. Its copyright status should be\n" +"// considered unchanged from the original VHDL.\n\n" + , stdout); + status = yyparse(); + fclose(stdout); + fclose(stdin); + if (status != 0 && strcmp(outfile,"-")!=0) unlink(outfile); + return status; +} diff --git a/translated_examples/based.v b/translated_examples/based.v new file mode 100644 index 0000000..ae85d73 --- /dev/null +++ b/translated_examples/based.v @@ -0,0 +1,39 @@ +// File based.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module based( +sysclk +); + +input sysclk; + +wire sysclk; + + +wire [31:0] foo; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16; + + assign foo = 123; + assign foo2 = 'B00101101110111; + assign foo8 = 'O0177362; + assign foo10 = 'D01234; + assign foo11 = 11#01234#; + assign foo16 = 'H12af; + +endmodule diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v new file mode 100644 index 0000000..bf88278 --- /dev/null +++ b/translated_examples/bigfile.v @@ -0,0 +1,501 @@ +// File bigfile.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// CONNECTIVITY DEFINITION +// no timescale needed + +module bigfile( +sysclk, +g_zaq_in, +g_aux, +scanb, +g_wrb, +g_rdb, +g_noop_clr, +swe_ed, +swe_lv, +din, +g_dout_w0x0f, +n9_bit_write, +reset, +alu_u, +debct_ping, +g_sys_in, +g_zaq_in_rst_hold, +g_zaq_hhh_enb, +g_zaq_out, +g_dout, +g_zaq_ctl, +g_zaq_qaz_hb, +g_zaq_qaz_lb, +gwerth, +g_noop, +g_vector, +swe_qaz1 +); + +// from external pins +input sysclk; +input [31:0] g_zaq_in; +input [31:0] g_aux; +input scanb; +input g_wrb; +input g_rdb; +input [31:0] g_noop_clr; +input swe_ed; +input swe_lv; +input [63:0] din; +input [4:0] g_dout_w0x0f; +input n9_bit_write; +// from reset_gen block +input reset; +input [31:0] alu_u; +input debct_ping; +output [31:0] g_sys_in; +output [31:0] g_zaq_in_rst_hold; +output [31:0] g_zaq_hhh_enb; +output [31:0] g_zaq_out; +output [31:0] g_dout; +output [31:0] g_zaq_ctl; +output [31:0] g_zaq_qaz_hb; +output [31:0] g_zaq_qaz_lb; +output [31:0] gwerth; +output [31:0] g_noop; +output [8 * 32 - 1:0] g_vector; +output [31:0] swe_qaz1; + +wire sysclk; +wire [31:0] g_zaq_in; +wire [31:0] g_aux; +wire scanb; +wire g_wrb; +wire g_rdb; +wire [31:0] g_noop_clr; +wire swe_ed; +wire swe_lv; +wire [63:0] din; +wire [4:0] g_dout_w0x0f; +wire n9_bit_write; +wire reset; +wire [31:0] alu_u; +wire debct_ping; +wire [31:0] g_sys_in; +wire [31:0] g_zaq_in_rst_hold; +wire [31:0] g_zaq_hhh_enb; +wire [31:0] g_zaq_out; +wire [31:0] g_dout; +wire [31:0] g_zaq_ctl; +wire [31:0] g_zaq_qaz_hb; +wire [31:0] g_zaq_qaz_lb; +reg [31:0] gwerth; +wire [31:0] g_noop; +reg [8 * 32 - 1:0] g_vector; +reg [31:0] swe_qaz1; + + +// IMPLEMENTATION +// constants +parameter g_t_klim_w0x0f = 5'b 00000; +parameter g_t_u_w0x0f = 5'b 00001; +parameter g_t_l_w0x0f = 5'b 00010; +parameter g_t_hhh_l_w0x0f = 5'b 00011; +parameter g_t_jkl_sink_l_w0x0f = 5'b 00100; +parameter g_secondary_t_l_w0x0f = 5'b 00101; +parameter g_style_c_l_w0x0f = 5'b 00110; +parameter g_e_z_w0x0f = 5'b 00111; +parameter g_n_both_qbars_l_w0x0f = 5'b 01000; +parameter g_style_vfr_w0x0f = 5'b 01001; +parameter g_style_klim_w0x0f = 5'b 01010; +parameter g_unklimed_style_vfr_w0x0f = 5'b 01011; +parameter g_style_t_y_w0x0f = 5'b 01100; +parameter g_n_l_w0x0f = 5'b 01101; +parameter g_n_vfr_w0x0f = 5'b 01110; +parameter g_e_n_r_w0x0f = 5'b 01111; +parameter g_n_r_bne_w0x0f = 5'b 10000; +parameter g_n_div_rebeq_w0x0f = 5'b 10001; +parameter g_alu_l_w0x0f = 5'b 10010; +parameter g_t_qaz_mult_low_w0x0f = 5'b 10011; +parameter g_t_qaz_mult_high_w0x0f = 5'b 10100; +parameter gwerthernal_style_u_w0x0f = 5'b 10101; +parameter gwerthernal_style_l_w0x0f = 5'b 10110; +parameter g_style_main_reset_hold_w0x0f = 5'b 10111; // comment +reg [31:0] g_t_klim_dout; +reg [31:0] g_t_u_dout; +reg [31:0] g_t_l_dout; +reg [31:0] g_t_hhh_l_dout; +reg [31:0] g_t_jkl_sink_l_dout; +reg [31:0] g_secondary_t_l_dout; +reg [3:0] g_style_c_l_dout; // not used +reg [31:0] g_e_z_dout; +reg [31:0] g_n_both_qbars_l_dout; +wire [31:0] g_style_vfr_dout; +reg [31:0] g_style_klim_dout; +wire [31:0] g_unklimed_style_vfr_dout; +reg [31:0] g_style_t_y_dout; +reg [31:0] g_n_l_dout; +reg [31:0] g_n_vfr_dout; +reg [31:0] g_e_n_r_dout; +reg g_n_r_bne_dout; +reg [31:0] g_n_div_rebeq_dout; +reg [31:0] g_alu_l_dout; +reg [31:0] g_t_qaz_mult_low_dout; +reg [31:0] g_t_qaz_mult_high_dout; +reg [31:0] gwerthernal_style_u_dout; +reg [31:0] gwerthernal_style_l_dout; +reg [31:0] g_style_main_reset_hold_dout; // other +reg [31:0] q_g_zaq_in; +reg [31:0] q2_g_zaq_in; +reg [31:0] q3_g_zaq_in; +reg [3:0] q_g_zaq_in_cd; +reg [31:0] q_g_style_vfr_dout; +reg [3:0] q_g_unzq; // i +wire [31:0] g_n_active; // inter +wire [31:0] g_zaq_in_y; +wire [31:0] g_zaq_in_y_no_dout; +wire [31:0] g_zaq_out_i; +wire [31:0] g_zaq_ctl_i; +wire [31:0] g_sys_in_i; +wire [31:0] g_sys_in_ii; +wire [31:0] g_dout_i; + + // qaz out + assign g_zaq_out_i = ((g_secondary_t_l_dout & ((g_aux ^ g_style_t_y_dout)))) | ((g_alu_l_dout & alu_u & ~g_secondary_t_l_dout)) | (( ~g_alu_l_dout & ~g_secondary_t_l_dout & g_t_u_dout)); + // Changed + assign g_zaq_out = g_zaq_out_i & ~g_t_jkl_sink_l_dout; + // qaz + // JLB + assign g_zaq_ctl_i = ~((((g_t_l_dout & ~g_t_jkl_sink_l_dout)) | ((g_t_l_dout & g_t_jkl_sink_l_dout & ~g_zaq_out_i)))); + // mux + //vnavigatoroff + assign g_zaq_ctl = scanb == 1'b 1 ? g_zaq_ctl_i : 32'b 00000000000000000000000000000000; + //vnavigatoron + assign g_zaq_hhh_enb = ~((g_t_hhh_l_dout)); + assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout; + assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout; + // Dout + assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b 0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b 0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b 00000000000000000000000000000000; + assign g_dout = g_rdb == 1'b 0 ? g_dout_i : {32{1'b1}}; + // this can be used to use zzz1 + always @(posedge sysclk) begin + if((scanb == 1'b 1)) begin + if((reset == 1'b 1)) begin + g_style_main_reset_hold_dout <= g_zaq_in; + end + //vnavigatoroff + end + else begin + g_style_main_reset_hold_dout <= q2_g_zaq_in; + end + //vnavigatoron + end + + // qaz + assign g_zaq_in_rst_hold = g_style_main_reset_hold_dout; + // Din + always @(posedge reset or posedge sysclk) begin : P2 + reg [4:0] g_dout_w0x0f_v; + + if((reset != 1'b 0)) begin + g_t_klim_dout <= {32{1'b0}}; + g_t_u_dout <= {32{1'b0}}; + g_t_l_dout <= {32{1'b0}}; + g_t_hhh_l_dout <= {32{1'b0}}; + g_t_jkl_sink_l_dout <= {32{1'b0}}; + g_secondary_t_l_dout <= {32{1'b0}}; + g_style_c_l_dout <= {4{1'b0}}; + g_e_z_dout <= {32{1'b0}}; + g_n_both_qbars_l_dout <= {32{1'b0}}; + g_style_klim_dout <= {32{1'b0}}; + g_style_t_y_dout <= {32{1'b0}}; + g_n_l_dout <= {32{1'b0}}; + g_e_n_r_dout <= {32{1'b0}}; + g_n_r_bne_dout <= 1'b 0; + g_n_div_rebeq_dout <= {32{1'b1}}; + g_alu_l_dout <= {32{1'b0}}; + g_t_qaz_mult_low_dout <= {32{1'b1}}; + // NOTE Low + g_t_qaz_mult_high_dout <= {32{1'b0}}; + gwerthernal_style_u_dout <= {32{1'b0}}; + gwerthernal_style_l_dout <= {32{1'b0}}; + end else begin + // clear + g_n_div_rebeq_dout <= g_n_div_rebeq_dout & ~g_noop_clr; + if((g_wrb == 1'b 0)) begin + // because we now... + for (i=0; i <= 1; i = i + 1) begin + if((i == 0)) begin + g_dout_w0x0f_v = g_dout_w0x0f; + end + else if((i == 1)) begin + if((n9_bit_write == 1'b 1)) begin + // set + g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b 1}; + end + else begin + disable; //VHD2VL: add block name here + end + //vnavigatoroff + end + else begin + // not possible but added for code coverage's sake + end + //vnavigatoron + case(g_dout_w0x0f_v) + g_t_klim_w0x0f : begin + g_t_klim_dout <= din[i * 32 + 31:i * 32]; + end + g_t_u_w0x0f : begin + // output klim + for (j=0; j <= 31; j = j + 1) begin + if(((g_t_klim_dout[j] == 1'b 0 && n9_bit_write == 1'b 0) || (din[j] == 1'b 0 && n9_bit_write == 1'b 1))) begin + g_t_u_dout[j] <= din[32 * i + j]; + end + end + end + g_t_l_w0x0f : begin + g_t_l_dout <= din[i * 32 + 31:i * 32]; + end + g_t_hhh_l_w0x0f : begin + g_t_hhh_l_dout <= din[i * 32 + 31:i * 32]; + end + g_t_jkl_sink_l_w0x0f : begin + g_t_jkl_sink_l_dout <= din[i * 32 + 31:i * 32]; + end + g_secondary_t_l_w0x0f : begin + g_secondary_t_l_dout <= din[i * 32 + 31:i * 32]; + end + g_style_c_l_w0x0f : begin + g_style_c_l_dout[3:0] <= din[3 + i * 32:i * 32]; + end + g_e_z_w0x0f : begin + g_e_z_dout <= din[i * 32 + 31:i * 32]; + end + g_n_both_qbars_l_w0x0f : begin + g_n_both_qbars_l_dout <= din[i * 32 + 31:i * 32]; + end + g_style_vfr_w0x0f : begin + // read-only register + end + g_style_klim_w0x0f : begin + g_style_klim_dout <= din[i * 32 + 31:i * 32]; + end + g_unklimed_style_vfr_w0x0f : begin + // read-only register + end + g_style_t_y_w0x0f : begin + g_style_t_y_dout <= din[i * 32 + 31:i * 32]; + end + g_n_l_w0x0f : begin + g_n_l_dout <= din[i * 32 + 31:i * 32]; + end + g_n_vfr_w0x0f : begin + // writes + end + g_e_n_r_w0x0f : begin + g_e_n_r_dout <= din[i * 32 + 31:i * 32]; + end + g_n_r_bne_w0x0f : begin + g_n_r_bne_dout <= din[i * 32]; + end + g_n_div_rebeq_w0x0f : begin + g_n_div_rebeq_dout <= din[i * 32 + 31:i * 32] | g_n_div_rebeq_dout; + // a '1' writes + end + g_alu_l_w0x0f : begin + g_alu_l_dout <= din[i * 32 + 31:i * 32]; + end + g_t_qaz_mult_low_w0x0f : begin + g_t_qaz_mult_low_dout <= din[i * 32 + 31:i * 32]; + end + g_t_qaz_mult_high_w0x0f : begin + g_t_qaz_mult_high_dout <= din[i * 32 + 31:i * 32]; + end + gwerthernal_style_u_w0x0f : begin + gwerthernal_style_u_dout <= din[i * 32 + 31:i * 32]; + end + gwerthernal_style_l_w0x0f : begin + gwerthernal_style_l_dout <= din[i * 32 + 31:i * 32]; + //vnavigatoroff + end + default : begin + //vnavigatoron + end + endcase + end + end + end + end + + // sample + always @(posedge reset or posedge sysclk) begin + if((reset != 1'b 0)) begin + q_g_zaq_in <= {32{1'b0}}; + q2_g_zaq_in <= {32{1'b0}}; + q3_g_zaq_in <= {32{1'b0}}; + end else begin + q_g_zaq_in <= g_zaq_in; + q2_g_zaq_in <= q_g_zaq_in; + q3_g_zaq_in <= g_zaq_in_y; + end + end + + // vfr register + assign g_unklimed_style_vfr_dout = q2_g_zaq_in; + // switch + assign g_zaq_in_y = g_style_t_y_dout ^ q2_g_zaq_in; + // qaz + assign g_style_vfr_dout = {g_zaq_in_y[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])))}; + // in scan mode + assign g_zaq_in_y_no_dout = scanb == 1'b 1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout; + //vnavigatoron + assign g_sys_in_i = ({g_zaq_in_y_no_dout[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])))}); + assign g_sys_in_ii = ((g_sys_in_i & ~gwerthernal_style_l_dout)) | ((gwerthernal_style_u_dout & gwerthernal_style_l_dout)); + assign g_sys_in = g_sys_in_ii; + always @(posedge reset or posedge sysclk) begin + if((reset != 1'b 0)) begin + q_g_zaq_in_cd <= {4{1'b0}}; + q_g_unzq <= {4{1'b1}}; + end else begin + // sample + if((debct_ping == 1'b 1)) begin + // taken + for (i=0; i <= 3; i = i + 1) begin + if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin + q_g_unzq[i] <= 1'b 1; + end + else begin + if((q_g_unzq[i] == 1'b 0)) begin + q_g_zaq_in_cd[i] <= g_zaq_in_y[i]; + end + else begin + q_g_unzq[i] <= 1'b 0; + end + end + end + end + else begin + for (i=0; i <= 3; i = i + 1) begin + if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin + q_g_unzq[i] <= 1'b 1; + end + end + end + end + end + + // generate lqqs + always @(posedge reset or posedge sysclk) begin + if((reset != 1'b 0)) begin + q_g_style_vfr_dout <= {32{1'b0}}; + end else begin + if((scanb == 1'b 1)) begin + q_g_style_vfr_dout <= g_style_vfr_dout; + //vnavigatoroff + end + else begin + // in scan + q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b 0,g_zaq_out_i[15:1],1'b 0}) | g_zaq_ctl_i | g_sys_in_ii; + end + //vnavigatoron + end + end + + // generate + assign g_n_active = (((((q_g_style_vfr_dout & ~g_style_vfr_dout)) | (( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout))))) & g_n_l_dout; + // check for lqq active and set lqq vfr register + // also clear + always @(posedge reset or posedge sysclk) begin + if((reset != 1'b 0)) begin + g_n_vfr_dout <= {32{1'b0}}; + gwerth <= {32{1'b0}}; + end else begin + for (i=0; i <= 31; i = i + 1) begin + // lqq + // vfr matches + if((g_n_active[i] == 1'b 1)) begin + gwerth[i] <= 1'b 1; + if((g_e_z_dout[i] == 1'b 1)) begin + // lqq + g_n_vfr_dout[i] <= 1'b 1; + end + else begin + g_n_vfr_dout[i] <= q_g_style_vfr_dout[i]; + end + end + else begin + // clear + if((g_e_z_dout[i] == 1'b 0)) begin + g_n_vfr_dout[i] <= q_g_style_vfr_dout[i]; + // default always assign + // in both + if((g_n_both_qbars_l_dout[i] == 1'b 1 || g_style_vfr_dout[i] == 1'b 1)) begin + gwerth[i] <= 1'b 0; + end + end + else begin + // write + if((g_wrb == 1'b 0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b 1)) begin + gwerth[i] <= 1'b 0; + g_n_vfr_dout[i] <= 1'b 0; + end + end + end + end + end + end + + //-- + // Create the Lqq + always @(g_n_r_bne_dout or g_e_n_r_dout) begin : P1 + reg [31:0] imod8, idiv8; + + for (i=0; i <= 31; i = i + 1) begin + imod8 = i % 8; + idiv8 = i / 8; + if((g_n_r_bne_dout == 1'b 0)) begin + // non-unique + g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8]; + end + else begin + // unique + if((imod8 == 0)) begin + g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8]; + end + else begin + g_vector[8 * i + 7:8 * i] <= (((g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8])) + ((imod8))); + end + end + end + end + + //-- + // Qaz + assign g_noop = g_n_div_rebeq_dout; + always @(swe_ed or swe_lv or g_e_z_dout) begin + for (i=0; i <= 31; i = i + 1) begin + if((g_e_z_dout[i] == 1'b 1)) begin + swe_qaz1[i] <= swe_ed; + end + else begin + swe_qaz1[i] <= swe_lv; + end + end + end + + +endmodule diff --git a/translated_examples/clk.v b/translated_examples/clk.v new file mode 100644 index 0000000..4f87cdb --- /dev/null +++ b/translated_examples/clk.v @@ -0,0 +1,72 @@ +// File clk.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module clk( +reset, +preset, +qreset, +sysclk, +dsysclk, +esysclk, +ival +); + +input reset, preset, qreset, sysclk, dsysclk, esysclk; +input [31:0] ival; + +wire reset; +wire preset; +wire qreset; +wire sysclk; +wire dsysclk; +wire esysclk; +wire [31:0] ival; + + +reg [10 + 3:0] foo; +reg [2:0] baz; +reg [4:7 - 1] egg; + + always @(posedge reset or posedge sysclk) begin + if((reset != 1'b 0)) begin + foo <= {(((10 + 3))-((0))+1){1'b1}}; + end else begin + foo <= ival[31:31 - ((10 + 3))]; + end + end + + always @(negedge preset or negedge dsysclk) begin + if((preset != 1'b 1)) begin + baz <= {3{1'b0}}; + end else begin + baz <= ival[2:0]; + end + end + + always @(negedge qreset or negedge esysclk) begin + if((qreset != 1'b 1)) begin + egg <= {(((7 - 1))-((4))+1){1'b0}}; + end else begin + egg <= ival[6:4]; + end + end + + +endmodule diff --git a/translated_examples/counters.v b/translated_examples/counters.v new file mode 100644 index 0000000..39f72b9 --- /dev/null +++ b/translated_examples/counters.v @@ -0,0 +1,449 @@ +// File counters.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module counters( +sysclk, +foo_card, +wfoo0_baz, +wfoo0_blrb, +wfoo0_zz1pb, +wfoo0_turn, +debct_baz, +debct_blrb, +debct_zz1pb, +debct_bar, +debct_turn, +Z0_bar, +Z0_baz, +Z0_blrb, +Z0_zz1pb, +Z0_turn, +Y1_bar, +Y1_baz, +Y1_blrb, +Y1_zz1pb, +Y1_turn, +X2_bar, +X2_baz, +X2_blrb, +X2_zz1pb, +X2_turn, +W3_bar, +W3_baz, +W3_blrb, +W3_zz1pb, +W3_turn, +Z0_cwm, +Z0, +Y1_cwm, +Y1, +X2_cwm, +X2, +W3_cwm, +W3, +wfoo0_cwm, +wfoo0_llwln, +debct_cwm, +debct_pull, +debct, +wdfilecardA2P +); + +input sysclk; +input foo_card; +input wfoo0_baz; +input wfoo0_blrb; +input wfoo0_zz1pb; +input [31:0] wfoo0_turn; +input debct_baz; +input debct_blrb; +input debct_zz1pb; +input debct_bar; +input [31:0] debct_turn; +input Z0_bar; +input Z0_baz; +input Z0_blrb; +input Z0_zz1pb; +input [31:0] Z0_turn; +input Y1_bar; +input Y1_baz; +input Y1_blrb; +input Y1_zz1pb; +input [31:0] Y1_turn; +input X2_bar; +input X2_baz; +input X2_blrb; +input X2_zz1pb; +input [31:0] X2_turn; +input W3_bar; +input W3_baz; +input W3_blrb; +input W3_zz1pb; +input [31:0] W3_turn; +// to engine block +output Z0_cwm; +output [31:0] Z0; +output Y1_cwm; +output [31:0] Y1; +output X2_cwm; +output [31:0] X2; +output W3_cwm; +output [31:0] W3; +output wfoo0_cwm; +output [31:0] wfoo0_llwln; +output debct_cwm; +output debct_pull; +output [31:0] debct; +output wdfilecardA2P; + +wire sysclk; +wire foo_card; +wire wfoo0_baz; +wire wfoo0_blrb; +wire wfoo0_zz1pb; +wire [31:0] wfoo0_turn; +wire debct_baz; +wire debct_blrb; +wire debct_zz1pb; +wire debct_bar; +wire [31:0] debct_turn; +wire Z0_bar; +wire Z0_baz; +wire Z0_blrb; +wire Z0_zz1pb; +wire [31:0] Z0_turn; +wire Y1_bar; +wire Y1_baz; +wire Y1_blrb; +wire Y1_zz1pb; +wire [31:0] Y1_turn; +wire X2_bar; +wire X2_baz; +wire X2_blrb; +wire X2_zz1pb; +wire [31:0] X2_turn; +wire W3_bar; +wire W3_baz; +wire W3_blrb; +wire W3_zz1pb; +wire [31:0] W3_turn; +wire Z0_cwm; +wire [31:0] Z0; +wire Y1_cwm; +wire [31:0] Y1; +wire X2_cwm; +wire [31:0] X2; +wire W3_cwm; +wire [31:0] W3; +reg wfoo0_cwm; +wire [31:0] wfoo0_llwln; +wire debct_cwm; +reg debct_pull; +wire [31:0] debct; +wire wdfilecardA2P; + + +reg [31:0] wfoo0_llwln_var; +reg [31:0] debct_var; +reg [31:0] Z0_var; +reg [31:0] Y1_var; +reg [31:0] X2_var; +reg [31:0] W3_var; +reg main_wfoo0_cwm; +reg do_q3p_Z0; +reg do_q3p_Y1; +reg do_q3p_X2; +reg do_q3p_W3; +reg do_q3p_wfoo0; +reg do_q3p_debct; +reg Z0_cwm_i; +reg Y1_cwm_i; +reg X2_cwm_i; +reg W3_cwm_i; +reg debct_cwm_i; +reg file_card_i; +reg do_file_card_i; +reg prev_do_file_card; + + //--- + // form the outputs + assign wfoo0_llwln = (wfoo0_llwln_var); + assign debct = (debct_var); + assign Z0 = (Z0_var); + assign Y1 = (Y1_var); + assign X2 = (X2_var); + assign W3 = (W3_var); + assign Z0_cwm = Z0_cwm_i; + assign Y1_cwm = Y1_cwm_i; + assign X2_cwm = X2_cwm_i; + assign W3_cwm = W3_cwm_i; + assign debct_cwm = debct_cwm_i; + assign wdfilecardA2P = do_file_card_i; + always @(posedge foo_card or posedge sysclk) begin + if(foo_card == 1'b 1) begin + wfoo0_llwln_var <= {32{1'b0}}; + debct_var <= {32{1'b0}}; + Z0_var <= {32{1'b0}}; + Y1_var <= {32{1'b0}}; + X2_var <= {32{1'b0}}; + W3_var <= {32{1'b0}}; + wfoo0_cwm <= 1'b 0; + debct_cwm_i <= 1'b 0; + debct_pull <= 1'b 0; + Z0_cwm_i <= 1'b 0; + Y1_cwm_i <= 1'b 0; + X2_cwm_i <= 1'b 0; + W3_cwm_i <= 1'b 0; + main_wfoo0_cwm <= 1'b 0; + file_card_i <= 1'b 0; + do_q3p_wfoo0 <= 1'b 0; + do_file_card_i <= 1'b 0; + prev_do_file_card <= 1'b 0; + do_q3p_Z0 <= 1'b 0; + do_q3p_Y1 <= 1'b 0; + do_q3p_X2 <= 1'b 0; + do_q3p_W3 <= 1'b 0; + do_q3p_debct <= 1'b 0; + end else begin + // pull + debct_pull <= 1'b 0; + do_file_card_i <= 1'b 0; + //-- + // wfoo0 + if(wfoo0_baz == 1'b 1) begin + wfoo0_llwln_var <= (wfoo0_turn); + main_wfoo0_cwm <= 1'b 0; + if(wfoo0_llwln_var == 32'b 00000000000000000000000000000000) begin + do_q3p_wfoo0 <= 1'b 0; + end + else begin + do_q3p_wfoo0 <= 1'b 1; + end + end + else begin + if(do_q3p_wfoo0 == 1'b 1 && wfoo0_blrb == 1'b 1) begin + wfoo0_llwln_var <= wfoo0_llwln_var - 1; + if((wfoo0_llwln_var == 32'b 00000000000000000000000000000000)) begin + wfoo0_llwln_var <= (wfoo0_turn); + if(main_wfoo0_cwm == 1'b 0) begin + wfoo0_cwm <= 1'b 1; + main_wfoo0_cwm <= 1'b 1; + end + else begin + do_file_card_i <= 1'b 1; + do_q3p_wfoo0 <= 1'b 0; + end + end + end + end + if(wfoo0_zz1pb == 1'b 0) begin + wfoo0_cwm <= 1'b 0; + end + if(Z0_baz == 1'b 1) begin + // counter Baz + Z0_var <= (Z0_turn); + if(Z0_turn == 32'b 00000000000000000000000000000000) begin + do_q3p_Z0 <= 1'b 0; + end + else begin + do_q3p_Z0 <= 1'b 1; + end + end + else begin + if(do_q3p_Z0 == 1'b 1 && Z0_blrb == 1'b 1) begin + if(Z0_bar == 1'b 0) begin + if(Z0_cwm_i == 1'b 0) begin + if(do_q3p_Z0 == 1'b 1) begin + Z0_var <= Z0_var - 1; + if((Z0_var == 32'b 00000000000000000000000000000001)) begin + Z0_cwm_i <= 1'b 1; + do_q3p_Z0 <= 1'b 0; + end + end + end + end + else begin + Z0_var <= Z0_var - 1; + if((Z0_var == 32'b 00000000000000000000000000000000)) begin + Z0_cwm_i <= 1'b 1; + Z0_var <= (Z0_turn); + end + end + // Z0_bar + end + end + // Z0_blrb + if(Z0_zz1pb == 1'b 0) begin + Z0_cwm_i <= 1'b 0; + end + if(Y1_baz == 1'b 1) begin + // counter Baz + Y1_var <= (Y1_turn); + if(Y1_turn == 32'b 00000000000000000000000000000000) begin + do_q3p_Y1 <= 1'b 0; + end + else begin + do_q3p_Y1 <= 1'b 1; + end + end + else if(do_q3p_Y1 == 1'b 1 && Y1_blrb == 1'b 1) begin + if(Y1_bar == 1'b 0) begin + if(Y1_cwm_i == 1'b 0) begin + if(do_q3p_Y1 == 1'b 1) begin + Y1_var <= Y1_var - 1; + if((Y1_var == 32'b 00000000000000000000000000000001)) begin + Y1_cwm_i <= 1'b 1; + do_q3p_Y1 <= 1'b 0; + end + end + end + end + else begin + Y1_var <= Y1_var - 1; + if((Y1_var == 32'b 00000000000000000000000000000000)) begin + Y1_cwm_i <= 1'b 1; + Y1_var <= (Y1_turn); + end + end + // Y1_bar + end + // Y1_blrb + if(Y1_zz1pb == 1'b 0) begin + Y1_cwm_i <= 1'b 0; + end + if(X2_baz == 1'b 1) begin + // counter Baz + X2_var <= (X2_turn); + if(X2_turn == 32'b 00000000000000000000000000000000) begin + do_q3p_X2 <= 1'b 0; + end + else begin + do_q3p_X2 <= 1'b 1; + end + end + else if(do_q3p_X2 == 1'b 1 && X2_blrb == 1'b 1) begin + if(X2_bar == 1'b 0) begin + if(X2_cwm_i == 1'b 0) begin + if(do_q3p_X2 == 1'b 1) begin + X2_var <= X2_var - 1; + if((X2_var == 32'b 00000000000000000000000000000001)) begin + X2_cwm_i <= 1'b 1; + do_q3p_X2 <= 1'b 0; + end + end + end + end + else begin + X2_var <= X2_var - 1; + if((X2_var == 32'b 00000000000000000000000000000000)) begin + //{ + X2_cwm_i <= 1'b 1; + X2_var <= (X2_turn); + end + end + //X2_bar + end + // X2_blrb + if(X2_zz1pb == 1'b 0) begin + X2_cwm_i <= 1'b 0; + end + if(W3_baz == 1'b 1) begin + // counter Baz + W3_var <= (W3_turn); + if(W3_turn == 32'b 00000000000000000000000000000000) begin + do_q3p_W3 <= 1'b 0; + end + else begin + do_q3p_W3 <= 1'b 1; + end + end + else if(do_q3p_W3 == 1'b 1 && W3_blrb == 1'b 1) begin + if(W3_bar == 1'b 0) begin + if(W3_cwm_i == 1'b 0) begin + if(do_q3p_W3 == 1'b 1) begin + W3_var <= W3_var - 1; + if((W3_var == 32'b 00000000000000000000000000000001)) begin + W3_cwm_i <= 1'b 1; + do_q3p_W3 <= 1'b 0; + end + end + end + end + else begin + W3_var <= W3_var - 1; + if((W3_var == 32'b 00000000000000000000000000000000)) begin + //{ + W3_cwm_i <= 1'b 1; + W3_var <= (W3_turn); + end + end + // W3_bar + end + // W3_blrb + if(W3_zz1pb == 1'b 0) begin + W3_cwm_i <= 1'b 0; + end + if(debct_baz == 1'b 1) begin + // counter Baz + debct_var <= (debct_turn); + if(debct_turn == 32'b 00000000000000000000000000000000) begin + do_q3p_debct <= 1'b 0; + end + else begin + do_q3p_debct <= 1'b 1; + end + end + else if(do_q3p_debct == 1'b 1 && debct_blrb == 1'b 1) begin + if(debct_bar == 1'b 0) begin + if(debct_cwm_i == 1'b 0) begin + if(do_q3p_debct == 1'b 1) begin + debct_var <= debct_var - 1; + if((debct_var == 32'b 00000000000000000000000000000001)) begin + debct_cwm_i <= 1'b 1; + debct_pull <= 1'b 1; + do_q3p_debct <= 1'b 0; + end + end + end + end + else begin + //-- T + // Continue + debct_var <= debct_var - 1; + // ending + if((debct_var == 32'b 00000000000000000000000000000000)) begin + //{ + debct_cwm_i <= 1'b 1; + debct_pull <= 1'b 1; + debct_var <= (debct_turn); + end + end + // debct_bar + end + // debct_blrb + // comment + if(debct_zz1pb == 1'b 0) begin + debct_cwm_i <= 1'b 0; + end + end + end + + +endmodule diff --git a/translated_examples/expr.v b/translated_examples/expr.v new file mode 100644 index 0000000..db4f962 --- /dev/null +++ b/translated_examples/expr.v @@ -0,0 +1,56 @@ +// File expr.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module expr( +reset, +sysclk, +ival +); + +input reset, sysclk, ival; + +wire reset; +wire sysclk; +wire ival; + + +reg [13:0] foo; +wire [2:0] baz; +reg [22:0] bam; +wire [5:3] out_i; +wire [8:0] input_status; +wire enable; wire debug; wire aux; wire outy; wire dv; wire value; + + // drive input status + assign input_status = {foo[9:4],((baz[3:0] & foo[3:0] | (( ~baz[3:0] & bam[3:0]))))}; + // drive based on foo + assign out_i = ((enable & ((aux ^ outy)))) | ((debug & dv & ~enable)) | (( ~debug & ~enable & value)); + // not drive + always @(negedge reset or negedge sysclk) begin + if((reset != 1'b 0)) begin + foo <= {14{1'b0}}; + end else begin + foo[3 * ((2 - 1))] <= (4 * ((1 + 2))); + bam[13:0] <= foo; + end + end + + +endmodule diff --git a/translated_examples/for.v b/translated_examples/for.v new file mode 100644 index 0000000..5d7141a --- /dev/null +++ b/translated_examples/for.v @@ -0,0 +1,61 @@ +// File for.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module forp( +reset, +sysclk +); + +input reset, sysclk; + +wire reset; +wire sysclk; + + +reg selection; +reg [6:0] egg_timer; + + always @(posedge reset or posedge sysclk) begin : P1 + reg [31:0] timer_var = 0; + reg [31:0] a, i, j, k; + reg [31:0] zz5; + reg [511:0] zz; + + if(reset == 1'b 1) begin + selection <= 1'b 1; + timer_var = 2; + egg_timer <= {7{1'b0}}; + end else begin + // pulse only lasts for once cycle + selection <= 1'b 0; + egg_timer <= {7{1'b1}}; + for (i=0; i <= j * k; i = i + 1) begin + a = a + i; + for (k=a - 9; k >= -14; k = k - 1) begin + zz5 = zz[31 + k:k]; + end + // k + end + // i + end + end + + +endmodule diff --git a/translated_examples/generate.v b/translated_examples/generate.v new file mode 100644 index 0000000..10af474 --- /dev/null +++ b/translated_examples/generate.v @@ -0,0 +1,66 @@ +// File generate.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module gen( +sysclk, +reset, +wrb, +din, +rdout +); + +parameter [31:0] bus_width=15; +parameter [31:0] TOP_GP2=0; +input sysclk, reset, wrb; +input [bus_width:0] din; +output [bus_width:0] rdout; + +wire sysclk; +wire reset; +wire wrb; +wire [bus_width:0] din; +wire [bus_width:0] rdout; + + +reg [bus_width * 2:0] regSelect; + + //--------------------------------------------------- + // Reg : GP 2 + // Active : 32 + // Type : RW + //--------------------------------------------------- + genvar bitnum; + generate for (bitnum=0; bitnum <= bus_width; bitnum = bitnum + 1) begin + wbit1 wbit1_inst( + .clk(sysclk), + .wrb(wrb), + .reset(reset), + .enb(regSelect[TOP_GP2]), + .din(din[bitnum]), + .dout(rdout[bitnum])); + + end + endgenerate + always @(posedge sysclk) begin + regSelect[1] <= 1'b 1; + end + + +endmodule diff --git a/translated_examples/generic.v b/translated_examples/generic.v new file mode 100644 index 0000000..42a6bee --- /dev/null +++ b/translated_examples/generic.v @@ -0,0 +1,70 @@ +// File generic.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module test( +reset, +sysclk, +a, +b, +enf, +load, +qtd, +base +); + +parameter [7:0] dog_width=8'b 10101100; +parameter [31:0] bus_width=32; +input reset, sysclk; +input [bus_width:0] a, b, enf, load, qtd, base; + +wire reset; +wire sysclk; +wire [bus_width:0] a; +wire [bus_width:0] b; +wire [bus_width:0] enf; +wire [bus_width:0] load; +wire [bus_width:0] qtd; +wire [bus_width:0] base; + + +wire [1 + 1:0] foo; +reg [9:0] code; wire [9:0] code1; +wire [324:401] egg; +wire [bus_width * 3 - 1:bus_width * 4] baz; +wire [31:0] complex; + + // Example of with statement + always @(*) begin + case(foo[2:0]) + 3'b 000,3'b 110 : code[9:2] <= {3'b 110,egg[325:329]}; + 3'b 101 : code[9:2] <= 8'b 11100010; + 3'b 010 : code[9:2] <= {1{1'b1}}; + 3'b 011 : code[9:2] <= {1{1'b0}}; + default : code[9:2] <= a + b + 1'b 1; + endcase + end + + assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); + assign foo = {(((1 + 1))-((0))+1){1'b0}}; + assign egg = {78{1'b0}}; + assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}}; + assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001}; + +endmodule diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v new file mode 100644 index 0000000..8551499 --- /dev/null +++ b/translated_examples/genericmap.v @@ -0,0 +1,128 @@ +// File genericmap.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module test( +clk, +rstn, +en, +start_dec, +addr, +din, +we, +pixel_in, +pix_req, +config, +bip, +a, +b, +c, +load, +pack, +base, +qtd, +dout, +pixel_out, +pixel_valid, +code, +complex, +eno +); + +parameter rst_val=1'b 0; +parameter [31:0] thing_size=201; +parameter [31:0] bus_width=201 % 32; +input clk, rstn; +input en, start_dec; +input [2:0] addr; +input [25:0] din; +input we; +input [7:0] pixel_in; +input pix_req; +input config, bip; +input [7:0] a, b; +input [7:0] c, load; +input [6:0] pack; +input [2:0] base; +input [21:0] qtd; +// Outputs +output [25:0] dout; +output [7:0] pixel_out; +output pixel_valid; +output [9:0] code; +output [23:0] complex; +output eno; + +wire clk; +wire rstn; +wire en; +wire start_dec; +wire [2:0] addr; +wire [25:0] din; +wire we; +wire [7:0] pixel_in; +wire pix_req; +wire config; +wire bip; +wire [7:0] a; +wire [7:0] b; +wire [7:0] c; +wire [7:0] load; +wire [6:0] pack; +wire [2:0] base; +wire [21:0] qtd; +wire [25:0] dout; +wire [7:0] pixel_out; +wire pixel_valid; +wire [9:0] code; +wire [23:0] complex; +wire eno; + + +wire [7:0] param; +wire selection; +wire start; wire enf; // Start and enable signals +wire [13:0] memdin; +wire [5:0] memaddr; +wire [13:0] memdout; +wire [1:0] colour; + + dsp dsp_inst0( + // Inputs + .clk(clk), + .rstn(rstn), + // Outputs + .dout(dout), + .memaddr(memaddr), + .memdout(memdout)); + + dsp #( + .rst_val(1'b 1), + .bus_width(16)) + dsp_inst1( + // Inputs + .clk(clk), + .rstn(rstn), + // Outputs + .dout(dout), + .memaddr(memaddr), + .memdout(memdout)); + + +endmodule diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v new file mode 100644 index 0000000..0ce47bd --- /dev/null +++ b/translated_examples/ifchain.v @@ -0,0 +1,43 @@ +// File ifchain.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// no timescale needed + +module test( +clk, +rstn +); + +input clk, rstn; + +wire clk; +wire rstn; + + +wire [3:0] a; +wire [3:0] b; +reg status; + + always @(posedge clk) begin + if({b[1],a[3:2]} == 3'b 001) begin + status <= 1'b 1; + end + end + + +endmodule diff --git a/translated_examples/test.v b/translated_examples/test.v new file mode 100644 index 0000000..f5e82aa --- /dev/null +++ b/translated_examples/test.v @@ -0,0 +1,242 @@ +// File test.vhd translated with vhd2vl v2.2 VHDL to Verilog RTL translator + +// vhd2vl is Free (libre) Software: +// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd +// http://www.ocean-logic.com +// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc +// Modifications Copyright (C) 2002, 2005, 2008, 2009 Larry Doolittle - LBNL +// http://doolittle.icarus.com/~larry/vhd2vl/ +// +// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting +// Verilog for correctness, ideally with a formal verification tool. +// +// You are welcome to redistribute vhd2vl under certain conditions. +// See the license (GPLv2) file included with the source for details. + +// The result of translation follows. Its copyright status should be +// considered unchanged from the original VHDL. + +// Project: VHDL to Verilog RTL translation +// Revision: 1.0 +// Date of last Revision: February 27 2001 +// Designer: Vincenzo Liguori +// vhd2vl test file +// This VHDL file exercises vhd2vl +// no timescale needed + +module test( +clk, +rstn, +en, +start_dec, +addr, +din, +we, +pixel_in, +pix_req, +config, +bip, +a, +b, +c, +load, +pack, +base, +qtd, +dout, +pixel_out, +pixel_valid, +code, +code1, +complex, +eno +); + +// Inputs +input clk, rstn; +input en, start_dec; +input [2:0] addr; +input [25:0] din; +input we; +input [7:0] pixel_in; +input pix_req; +input config, bip; +input [7:0] a, b; +input [7:0] c, load; +input [6:0] pack; +input [2:0] base; +input [21:0] qtd; +// Outputs +output [25:0] dout; +output [7:0] pixel_out; +output pixel_valid; +output [9:0] code; +output [9:0] code1; +output [23:0] complex; +output eno; + +wire clk; +wire rstn; +wire en; +wire start_dec; +wire [2:0] addr; +wire [25:0] din; +wire we; +wire [7:0] pixel_in; +wire pix_req; +wire config; +wire bip; +wire [7:0] a; +wire [7:0] b; +wire [7:0] c; +wire [7:0] load; +wire [6:0] pack; +wire [2:0] base; +wire [21:0] qtd; +wire [25:0] dout; +reg [7:0] pixel_out; +wire pixel_valid; +reg [9:0] code; +wire [9:0] code1; +wire [23:0] complex; +wire eno; + + +// Components declarations are ignored by vhd2vl +// but they are still parsed +parameter [1:0] + red = 0, + green = 1, + blue = 2, + yellow = 3; + +reg [1:0] status; +parameter PARAM1 = 8'b 01101101; +parameter PARAM2 = 8'b 11001101; +parameter PARAM3 = 8'b 00010111; +wire [7:0] param; +reg selection; +reg start; wire enf; // Start and enable signals +wire [13:0] memdin; +wire [5:0] memaddr; +wire [13:0] memdout; +reg [1:0] colour; + + assign param = config == 1'b 1 ? PARAM1 : status == green ? PARAM2 : PARAM3; + // Synchronously process + always @(posedge clk) begin + pixel_out <= pixel_in ^ 8'b 11001100; + end + + // Synchronous process + always @(posedge clk) begin + case(status) + red : begin + colour <= 2'b 00; + end + green : begin + colour <= 2'b 01; + end + blue : begin + colour <= 2'b 10; + end + default : begin + colour <= 2'b 11; + end + endcase + end + + // Synchronous process with asynch reset + always @(posedge clk or posedge rstn) begin + if(rstn == 1'b 0) begin + status <= red; + end else begin + case(status) + red : begin + if(pix_req == 1'b 1) begin + status <= green; + end + end + green : begin + if(a[3] == 1'b 1) begin + start <= start_dec; + status <= blue; + end + else if(({b[5],a[3:2]}) == 3'b 001) begin + status <= yellow; + end + end + blue : begin + status <= yellow; + end + default : begin + start <= 1'b 0; + status <= red; + end + endcase + end + end + + // Example of with statement + always @(*) begin + case(memaddr[2:0]) + 3'b 000,3'b 110 : code[9:2] <= {3'b 110,pack[6:2]}; + 3'b 101 : code[9:2] <= 8'b 11100010; + 3'b 010 : code[9:2] <= {1{1'b1}}; + 3'b 011 : code[9:2] <= {1{1'b0}}; + default : code[9:2] <= a + b + 1'b 1; + endcase + end + + assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); + // Asynch process + always @(we or addr or config or bip) begin + if(we == 1'b 1) begin + if(addr[2:0] == 3'b 100) begin + selection <= 1'b 1; + end + else if(({b,a}) == {a,b} && bip == 1'b 0) begin + selection <= config; + end + else begin + selection <= 1'b 1; + end + end + else begin + selection <= 1'b 0; + end + end + + // Components instantiation + dsp dsp_inst( + // Inputs + .clk(clk), + .rstn(rstn), + .en(en), + .start(start), + .param(param), + .addr(addr), + .din(din), + .we(we), + .memdin(memdin), + // Outputs + .dout(dout), + .memaddr(memaddr), + .memdout(memdout)); + + mem dsp_mem( + // Inputs + .clk(clk), + .rstn(rstn), + .en(en), + .cs(selection), + .addr(memaddr), + .din(memdout), + // Outputs + .dout(memdin)); + + assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001}; + assign enf = a == (7'b 1101111 + load) && c < 7'b 1000111 ? 1'b 1 : 1'b 0; + assign eno = enf; + +endmodule |