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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-12 21:37:55 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-14 22:01:08 -0300 |
| commit | 40194fa7f34b2130afe4be5d02b41cd56be0f3a5 (patch) | |
| tree | 0620767a9848a038b20ed22aabc65deb53c826de /examples/generate.vhd | |
| parent | fd94b98a5c5f7ec819511445bdcf4bbe34338b7b (diff) | |
| download | vhdl2vl-40194fa7f34b2130afe4be5d02b41cd56be0f3a5.tar.gz vhdl2vl-40194fa7f34b2130afe4be5d02b41cd56be0f3a5.zip | |
Added analysis of examples with GHDL
Some examples were corrected according GHDL complains.
Corresponding traslated_examples were modified.
Use of synopsys libraries was removed.
Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned').
The problem was comented.
Diffstat (limited to 'examples/generate.vhd')
| -rw-r--r-- | examples/generate.vhd | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/generate.vhd b/examples/generate.vhd index 56d5d3c..4abdbf6 100644 --- a/examples/generate.vhd +++ b/examples/generate.vhd @@ -1,5 +1,5 @@ LIBRARY IEEE; -USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +USE IEEE.std_logic_1164.all; entity gen is generic( bus_width : integer := 15; TOP_GP2 : integer:= 0 |
