| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add initial pre-PAR simulation framework from internal files | Raptor Engineering Development Team | 2019-03-14 | 1 | -3/+16 |
| * | Convert combinatorial logic to registered logic to work around apparent Yosys... | Raptor Engineering Development Team | 2018-01-12 | 1 | -1/+6 |
| * | Fix license template in Makefile | Raptor Engineering Development Team | 2018-01-07 | 1 | -3/+20 |
| * | Properly generate programming file | Raptor Engineering Development Team | 2017-12-30 | 1 | -2/+2 |
| * | Add initial Talos™ II front panel control logic | Raptor Engineering Development Team | 2017-12-30 | 1 | -2/+2 |
| * | Remove spurious power_sequencer.v file | Raptor Engineering Development Team | 2017-12-30 | 1 | -2/+2 |
| * | Initial buildable variant for Talos™ II | Raptor Engineering Development Team | 2017-12-30 | 1 | -0/+105 |
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index : talos-system-fpga | |
| Talos™ II FPGA sources | Raptor Computing Systems |
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