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| author | Raptor Engineering Development Team <support@raptorengineering.com> | 2017-12-30 18:34:14 -0600 |
|---|---|---|
| committer | Raptor Engineering Development Team <support@raptorengineering.com> | 2017-12-30 18:34:50 -0600 |
| commit | fc6e00ae5e6af2a8a5475cf7e977747003697837 (patch) | |
| tree | c723ed045589dfc8d7cff79448dfdc26b87d2917 /Makefile | |
| parent | 8c9f1099391f9c158b678d9a2259754ac64adc78 (diff) | |
| download | talos-system-fpga-fc6e00ae5e6af2a8a5475cf7e977747003697837.tar.gz talos-system-fpga-fc6e00ae5e6af2a8a5475cf7e977747003697837.zip | |
Add initial Talos™ II front panel control logic
Add initial Talos™ II system control logic
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -22,11 +22,11 @@ YOSYS_ICE40_SIM_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v) .PRECIOUS: system_fpga_%.int -system_fpga_%.tmg: system_fpga_%.int +system_fpga_%.tmg: system_fpga_%.int system_fpga.pcf echo "Total path delay: inf ns (0.0 MHz)" > $@ -icetime -tmd hx1k -p system_fpga.pcf -P vq100 $< > $@ 2>&1 -system_fpga_%.int: system_fpga.blif +system_fpga_%.int: system_fpga.blif system_fpga.pcf echo "" > $@ -arachne-pnr -s $* -d 1k -P vq100 -m $(MAX_FPGA_ROUTE_PASSES) -p system_fpga.pcf $< -o $@ |
