diff options
Diffstat (limited to 'main.v')
-rw-r--r-- | main.v | 54 |
1 files changed, 16 insertions, 38 deletions
@@ -1,11 +1,18 @@ // Copyright © 2017, International Business Machines Corp. -// Copyright © 2017 - 2018 Raptor Engineering, LLC +// Copyright © 2017 - 2019 Raptor Engineering, LLC // All Rights Reserved // // See LICENSE file for licensing details +// +// HARDWARE ERRATA NOTICE +// This version of the system FPGA will only function on hardware revision 1.01 or higher. +// If you have hardware revision 1.00, please use the talos-pcb-rev1.00 branch instead! module system_fpga_top ( + // FPGA clock + input wire fpga_clock, + // LPC clock input wire lpc_clock, @@ -232,7 +239,7 @@ module system_fpga_top reg [RAIL_SIZE - 1:0] pg_buf = 0; reg sysgood_buf = 1'b0; wire clk_in; - wire clk_in_lpc; + wire clk_in_fpga; wire clk_in_ring; wire stdby_sed = 1'b0; reg sysen_buf = 1'b0; @@ -302,41 +309,14 @@ module system_fpga_top reg hostboot_startup_fader_common_high = 1'b0; reg [7:0] led_override_request = 8'b00000000; - // Implement nasty ring oscillator for fallback use when main system clock is offline - // Thanks to Clifford Wolf for the idea and basic code! - wire chain_in; - wire chain_out; - wire [99:0] buffers_in; - wire [99:0] buffers_out; - assign buffers_in = {buffers_out[98:0], chain_in}; - assign chain_out = buffers_out[99]; - assign chain_in = !chain_out; - - SB_LUT4 #( - .LUT_INIT(16'd2) - ) buffers [99:0] ( - .O(buffers_out), - .I0(buffers_in), - .I1(1'b0), - .I2(1'b0), - .I3(1'b0) - ); - - // Divide unstable 10MHz ring clock down to ~2MHz - reg [2:0] ring_clock_divider = 0; - always @(posedge chain_out) begin - ring_clock_divider = ring_clock_divider + 1; + // Divide input 8MHz clock down to 1MHz + reg [2:0] fpga_clock_divider = 0; + always @(posedge fpga_clock) begin + fpga_clock_divider = fpga_clock_divider + 1; end - assign clk_in_ring = ring_clock_divider[2]; + assign clk_in_fpga = fpga_clock_divider[2]; - // Divide input 33MHz clock down to 4.125MHz - reg [2:0] lpc_clock_divider = 0; - always @(posedge lpc_clock) begin - lpc_clock_divider = lpc_clock_divider + 1; - end - assign clk_in_lpc = lpc_clock_divider[2]; - - // Divide 4.125MHz clock down to 500Hz, 125Hz, and 7Hz, respectively + // Divide 4MHz clock down to 488Hz, 122Hz, and 6Hz, respectively wire timer_clk_2; wire timer_clk_3; wire timer_clk_4; @@ -348,9 +328,7 @@ module system_fpga_top assign timer_clk_3 = timer_clk_counter[14]; assign timer_clk_4 = timer_clk_counter[16]; - reg clock_select = 1'b1; - - assign clk_in = (clock_select)?clk_in_ring:clk_in_lpc; + assign clk_in = clk_in_fpga; // I2C device i2c_slave #( |