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* vas: Set FIRs according to workbookMichael Neuling2017-08-221-7/+3
| | | | | | | | | | | This sets the FIR, FIR mask and FIR action registers according to VAS workbook v1.20. It also renames them to make it clear what they are. Without this any VAS error will checkstop the machine, rather than potentially be recoverable. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Track whether a PCI device is a virtual functionRussell Currey2017-08-211-0/+1
| | | | | | | | | | This can be checked from config space, but we will need to know this when restoring the PCI topology, and it is not always safe to access config space during this period. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Set mmio enable bits in DD2Sukadev Bhattiprolu2017-08-211-0/+3
| | | | | | | | | POWER9 DD2 added some new "enable" bits that must be set for VAS to work. These bits were unused in DD1. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Acked-By: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Enhanced PCIe training tracingMichael Neuling2017-08-111-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This add more details to the PCI training tracing (aka Rick Mata mode). It enables the PCIe Link Training and Status State Machine (LTSSM) tracing and details on speed and link width. Output now looks like this when enabled (via nvram): [ 1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling [ 1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling [ 1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery [ 1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery [ 1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery [ 1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0 [ 1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained GEN4:x16:L0 [ 1.141757964,3] PHB#0000[0:0]: TRACE: Link trained. [ 1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling [ 1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config [ 1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery [ 1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery [ 1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0 [ 1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained GEN3:x08:L0 [ 1.114854650,3] PHB#0001[0:1]: TRACE: Link trained. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Add xscom_write_mask() functionAlistair Popple2017-08-041-1/+1
| | | | | | | | | | It is common for xscom registers to only contain specific bit fields that need to be modified without altering the rest of the register. This adds a convenience function to perform xscom read-modify-write operations under a mask. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Set the XTS config2 registerReza Arbab2017-08-041-0/+1
| | | | | | | | | | | | | | | | POWER9 DD2 has added a new bit we'd like to set: "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush" This has passed sanity tests with 4.12 kernels, which are capable of exercising this capability. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Adjust content of the NTL BARReza Arbab2017-08-041-2/+4
| | | | | | | | | | Reflect the changed NTL BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Adjust content of the GENID BARReza Arbab2017-08-041-2/+3
| | | | | | | | | | Reflect the changed GENID BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add NPU2_GPU1_MEM_BARReza Arbab2017-08-041-0/+1
| | | | | | | | | | | | POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to program things the old way on DD1 systems. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Fix indirect SCOM addressesReza Arbab2017-08-041-2/+4
| | | | | | | | | | Change these values for POWER9 DD2, but keep backwards compatibility. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Enable PCI peer-to-peerFrederic Barrat2017-08-043-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NX: Add P9 NX support for gzip compression engineHaren Myneni2017-08-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,gzip-high-fifo : High priority gzip RxFIFO /ibm,gzip-normal-fifo : Normal priority gzip RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-gzip priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RxFIFO size lpid : 0xfff (1's for 12 bits in UMAC notify match register) pid : gzip coprocessor type tid : counter for gzip Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NX: Add P9 NX support for 842 compression engineHaren Myneni2017-08-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds changes needed for 842 compression engine on power 9. Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9 and the channel setup will be done with receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used for this setup. p9 NX supports high and normal priority FIFOs. skiboot is not involved to process data with 842 engine, but configures User Mode Access Control (UMAC) noitify match register with these values and export them to kernel with device-tree entries. Also configure registers to setup and enable / disable the engine with the appropriate registers. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX 842 engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,842-high-fifo : High priority 842 RxFIFO /ibm,842-normal-fifo : Normal priority 842 RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-842 priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RXFIFO size lpid : 0xfff (1's for 12 bits set in UMAC notify match register) pid : 842 coprocessor type tid : Counter for 842 Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NX: Organize NX compression code to include 842 and gzip supportHaren Myneni2017-08-011-3/+15
| | | | | | | | | | P9 NX also supports gzip compression. So this patch creates nx-compress.c and reorg nx-842.c code so that common functions that are needed for both 842 and gzip compression will be moved in to nx-compress.c. This patch does not change the actual functionality. Signed-off-by: Haren Myneni <hmyneni@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NX: Add P9 NX register defines for 842 / gzip enginesHaren Myneni2017-08-011-2/+86
| | | | | | | | | This patch adds defines for 842 / gzip engine registers introduced on P9 NX and their bit values. Some of these register defines will not be used in skiboot right now, but added to sync with existing defines in nx.h. Signed-off-by: Haren Myneni <hmyneni@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Define vas_get_wcbs_bar interfaceSukadev Bhattiprolu2017-08-011-0/+1
| | | | | | | | | Implement the function vas_get_wcbs_bar() that returns the Window Context Backing store address register. NX driver uses this function to initialize its UMAC Send WC register. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Define vas_get_hvwc_mmio_bar interfaceSukadev Bhattiprolu2017-08-011-0/+1
| | | | | | | | The nest accelerator (NX) will need this interface to initialize its UMAC MMIO BAR. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Initialize VAS registersSukadev Bhattiprolu2017-08-011-0/+3
| | | | | | | | | | Initialize the VAS registers on each of instance that we discover. Initializing VAS involves writing either pre-defined values or allocated addresses to appropriate SCOM addresses. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: update phys_map_get API usage] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Define macros of constants and register fieldsSukadev Bhattiprolu2017-08-011-0/+142
| | | | | | | | Define macros for the various Base Address Regions and Register fields that are needed by VAS. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Define helpers to extract P9 node/chip idsSukadev Bhattiprolu2017-08-011-0/+4
| | | | | | | | VAS needs the node and chip ids to compute the "paste address" of a window. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: occ: Add support to clear sensor groupsShilpasri G Bhat2017-07-282-1/+5
| | | | | | | | | | Adds a generic API to clear sensor groups. OCC inband sensor groups such as CSM, Profiler and Job Scheduler can be cleared using this API. It will clear the min/max of all sensors belonging to OCC sensor groups. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: occ: Add support for OCC inband sensorsShilpasri G Bhat2017-07-282-0/+5
| | | | | | | | | | | | | | | | | Add support to parse and export OCC inband sensors which are copied by OCC to main memory in P9. Each OCC writes three buffers which includes one names buffer for sensor meta data and two buffers for sensor readings. While OCC writes to one buffer the sensor values can be read from the other buffer. The sensors are updated every 100ms. This patch adds power, temperature, current and voltage sensors to /ibm,opal/sensors device-tree node which can be exported by the ibmpowernv-hwmon driver in Linux. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* psr: occ: Add support to change power-shifting-ratioShilpasri G Bhat2017-07-282-1/+49
| | | | | | | | | | | Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Documentation enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* powercap: occ: Add a generic powercap frameworkShilpasri G Bhat2017-07-282-1/+46
| | | | | | | | | | | This patch adds a generic powercap framework and exports OCC powercap sensors using which system powercap can be set inband through OPAL-OCC command-response interface. Documentation for powercap enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-msg: Increase the max-async completion count by max chips possibleShilpasri G Bhat2017-07-281-1/+1
| | | | | | | | | OPAL-OCC command-response framework will also use async requests. So bump up the max-async completion requests to accommodate maximum number of chips possible. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Add support for OPAL-OCC command/response interfaceShilpasri G Bhat2017-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a shared memory based command/response interface between OCC and OPAL. In HOMER, there is an OPAL command buffer and an OCC response buffer which is used to send inband commands to OCC. The OPAL-OCC command/response sequence is as follows: 1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready' bit in OPAL command flag are set to zero. If yes then proceed with below steps to send a command to OCC. 2. Write the command value, request ID and command specific data to the OPAL command buffer. 3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command flag to indicate command is ready. 4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit is set by OPAL. If the bit is set then OCC will set the 'OCC Progress' bit. 5. OCC will process the command and write the response to the OCC response buffer and set the 'Rsp Ready' bit in the response flag and sends an interrupt. 8. OPAL will receive the interrupt and queue the response to the host. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Be more conservative on link presence timeoutMichael Neuling2017-07-281-1/+1
| | | | | | | | | | | | | | | | In this patch we tuned our link timing to be more agressive: cf960e2884 phb4: Improve reset and link training timing Cards should take only 32ms but unfortunately we've seen some take up to 440ms. Hence bump our timer up to 1000ms. This can hurt boot times on systems where slots indicate a hotplug status but no electrical link is present (which we've seen). Since we have to wait 1 second between PERST and touching config space anyway, it shouldn't hurt too much. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Add link training trace modeMichael Neuling2017-07-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a mode to PHB4 to trace training process closely. This activates as soon as PERST is deasserted and produces human readable output of the process. This may increase training times since it duplicates some of the training code. This code has it's own simple checks for fence and timeout but will fall through to the default training code once done. Output produced, looks like the "TRACE:" lines below: [ 3.410799664,7] PHB#0001[0:1]: FRESET: Starts [ 3.410802000,7] PHB#0001[0:1]: FRESET: Prepare for link down [ 3.410806624,7] PHB#0001[0:1]: FRESET: Assert skipped [ 3.410808848,7] PHB#0001[0:1]: FRESET: Deassert [ 3.410812176,3] PHB#0001[0:1]: TRACE: 0x0000000101000000 0ms [ 3.417170176,3] PHB#0001[0:1]: TRACE: 0x0000100101000000 12ms presence [ 3.436289104,3] PHB#0001[0:1]: TRACE: 0x0000180101000000 49ms training [ 3.436373312,3] PHB#0001[0:1]: TRACE: 0x00001d0811000000 49ms trained [ 3.436420752,3] PHB#0001[0:1]: TRACE: Link trained. [ 3.436967856,7] PHB#0001[0:1]: LINK: Start polling [ 3.437482240,7] PHB#0001[0:1]: LINK: Electrical link detected [ 3.437996864,7] PHB#0001[0:1]: LINK: Link is up [ 4.438000048,7] PHB#0001[0:1]: LINK: Link is stable Enabled via nvram using: nvram -p ibm,skiboot --update-config pci-tracing=true Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Improve reset and link training timingMichael Neuling2017-07-252-2/+5
| | | | | | | | | | | | | | | | | | | This improves PHB reset and link training timing. Justifications and reasons are included in the patch. Polling frequencies are decreased from 100ms to 10ms. Added is a new state called PHB4_SLOT_LINK_STABLE which is now needed since the link training can be so fast that we touch config space too quickly (PCIe spec requires 1 second between PERST de-assert and device config space reads). We use this new state to sanity check the PHB and link before moving onto the PCI bus scan, where we no longer recover from these error conditions. Also added is simplified documentation of the PHB reset and training flow. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Fix comment around OPAL_IMC_COUNTERS_ enumMadhavan Srinivasan2017-07-171-1/+1
| | | | | | Fixes: 7801be0fcf2a2 ('skiboot: Add opal calls to init/start/stop IMC devices) Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* IPMI: Move MAX_IPMI_SENSORS macro to ipmi.hVasant Hegde2017-07-131-0/+2
| | | | | | | ..so that it can be used in other places as well. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Rework retries so we can do more than oneMichael Neuling2017-07-131-0/+1
| | | | | | | | | | This reworks the pci link training retry code so that we can do more than one retry. This will now also print an error if a link fails to train. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Enable memory backing of queuesBenjamin Herrenschmidt2017-07-121-0/+6
| | | | | | | | | This dedicates 6x64k pages of memory permanently for the XIVE to use for internal queue overflow. This allows the XIVE to deal with some corner cases where the internal queues might prove insufficient. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt2017-07-121-0/+7
| | | | | | | | Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Cleanup AMR and IAMR when re-initializing CPUsBenjamin Herrenschmidt2017-06-301-0/+2
| | | | | | | | | | | | | | | | | | There's a bug in current Linux kernels leaving crap in those registers accross kexec and not sanitizing them on boot. This breaks kexec under some circumstances (such as booting a hash kernel from a radix one on P9 DD2.0). The long term fix is in Linux, but this workaround is a reasonable way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus() and shouldn't have adverse effects. We could also use that same mechanism to cleanup other things as well such as restoring some other SPRs to their default value in the future. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix number of index bits in IODA tablesBenjamin Herrenschmidt2017-06-301-1/+1
| | | | | | | | | | | On PHB4 the number of index bits in the IODA table address register was bumped to 10 bits to accomodate for 1024 MSIs and 1024 TVEs (DD2). However our macro only defined the field to be 9 bits, thus causing "interesting" behaviours on some systems. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Use phys-map to get MMIO BARsAndrew Donnellan2017-06-301-0/+4
| | | | | | | | | | | Commit bdea201a4c4b ("hw/npu2.c: Use phys-map to get GPU memory BARs") added use of phys-map for setting GPU memory BARs. Move the MMIO BARs over to using phys-map as well. Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Handle combined units node in the imc dtMadhavan Srinivasan2017-06-271-0/+7
| | | | | | | | | | | | | | | | Add code to detect combined unit nodes in the imc device tree. Due to HW/OCC restriction mcs* units are paired and monitored by the nest microcode. Microcode today does not support monitoring of individual mcs* unit events, so the patch first remove these mcs* from the imc device tree if found. Secondly to enable or disbale combined units nodes like "mcs01", "mcs23","mcs45" and "mcs67", additional parser loop is added to disable_unavailable_units(). Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Add opal calls to init/start/stop IMC devicesAnju T Sudhakar2017-06-272-1/+20
| | | | | | | | | | | | | | | | | | | | | | | Add new opal calls to init, start and stop the IMC nest/core units. To initialize the core IMC counters, it takes a physical address per core as an input and writes that address to PDBAR[14:50] bits. It initializes the htm_mode and event_mask, where it selects the time interval at which the counter values must be posted to the given memory location and enables the counters to start running by setting the appropriate bits. To disable/enable the nest IMC counters (stop or resume counting), writes into "command" field of the nest control block in the reserve memory location. To disable/enable the core IMC counters (stop or resume counting), writes into appropriate bits of htm_mode to disable the counters. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt rather than hardcode IMC prefix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Find the IMC DTBMadhavan Srinivasan2017-06-273-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMC (In Memory Collection) catalog is a repository of information about the Performance Monitoring Units (PMUs) and their events under the IMC infrastructure. The information include : - The PMU names - Event names - Event description - Event offsets - Event scale - Event unit The catalog is provided as a flattened device tree (dtb). Processors with different PVR values may have different PMU or event names. Hence, for each processor, there can be multiple device tree binaries (dtbs) containing the IMC information. Each of the dtb is compressed and forms a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link to the commit adding this partition to PNOR : https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84 So, each compressed dtb forms a sub-partition inside the IMC pnor partition and can be accessed/loaded through a sub-partition id which is nothing but the PVR id. Based on the current processor's PVR, the appropriate sub-partion will be loaded. Note however, that the catalog information is in the form of a dtb and the dtb is compressed too. So, the sub-partition loaded must be decompressed first before we can actually use it. It is important to mention here that while a PNOR image built for one processor is specific to only that processor and isn't portable, a single system generation (Processor version) may have multiple revisions and these revisions may have some changes in their IMC PMUs and events, and hence, the need for multiple IMC DTBs. The sub-partition that we obtain from the IMC pnor partition is a compressed device tree binary. We uncompress it using the libxz's functions. After uncompressing it, we link the device tree binary to the system's device tree. The kernel can now access the device tree and get the IMC PMUs and their events' information. Not all the IMC PMUs listed in the device tree may be available. This is indicated by imc availability vector (which is a part of the IMC control block structure). We need to check this vector and make sure to remove the IMC device nodes which are unavailable. Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Nest IMC macro definitionsHemant Kumar2017-06-271-0/+119
| | | | | | | | | | | | | | | | | | Add the macros needed for Nest IMC (In Memory Collection) instrumentation support by creating a new file in include/ called "imc.h". Also, add a header "nest_imc.h" containing an array of possible list of nest PMUs. These macros are needed to discover the catalog subpartition, enable and disable the nest IMC instrumentation. Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> [Anju: changed NEST_IMC_RESUME to NEST_IMC_RUNNING] Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> [maddy: Removed nest_imc.h and updated few macros] Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dt: Add phandle fixup helpersMadhavan Srinivasan2017-06-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When there is a new device tree that needs to be added to the main dt of the opal (ex, IMC catalog dtb loaded from pnor partition), we need to check for the phandle values in the new incoming device tree before attaching it. Reason is that, incoming device tree could already have phandle values initialized for its nodes. Now, if we attach this new device tree to the main opal DT, we could potentially hit phandle duplicate error (since the phandles value usually start with 1). To avoid this, a new helper function dt_adjust_subtree_phandle() is added to scan the incoming device tree and update node "phandle" accordingly based on the opal "last_phandle" value. Add to this, helper function also supports updates of "properties" with in a node which may refer the "phandle" value in the incoming device tree. Helper function will also fix the "properties" field accordingly. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* dt: Add helper function for last_phandle updatesMadhavan Srinivasan2017-06-271-0/+16
| | | | | | | | | Add helper functions for "last_phandle" access/update and modify functions to use helper functions. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Support setting HID[RADIX] and set it by default on P9Benjamin Herrenschmidt2017-06-263-0/+11
| | | | | | | | | | | | | | | | | This adds new opal_reinit_cpus() flags to setup radix or hash mode in HID[8] on POWER9. By default HID[8] will be set. On P9 DD1.0, Linux will change it as needed. On P9 DD2.0 hash works in radix mode (radix is really "dual" mode) so KVM won't break and existing kernels will work. Newer kernels built for hash will call this to clear the HID bit and thus get the full size of the TLB as an optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Rework HILE changeBenjamin Herrenschmidt2017-06-261-1/+2
| | | | | | | | | Create a more generic helper for changing HID0 bits on all processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Make init_hid() local to cpu.cBenjamin Herrenschmidt2017-06-261-1/+0
| | | | | | | | | No point doing that from init on the main CPU while it's done already inside cpu.c for secondaries. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add "cleanup_global_tlb" for P9 and laterBenjamin Herrenschmidt2017-06-261-0/+1
| | | | | | | | | | | | | Uses broadcast TLBIE's to cleanup the TLB on all cores and on the nest MMU By default this works with older binutils but there is a version (in #defines) that requires newer binutils and which documents what the instructions are. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Rename cleanup_tlb() to cleanup_local_tlb()Benjamin Herrenschmidt2017-06-261-1/+1
| | | | | | | | It uses tlbiel and only cleans up the TLB of the calling core Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* psi: Use phys_map to setup the BARsBenjamin Herrenschmidt2017-06-261-1/+1
| | | | | | | | Removes the hard coded address and the useless warning Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Move IO VPD preload out to a common placeBenjamin Herrenschmidt2017-06-261-2/+1
| | | | | | | | | | | | The code is duplicated between phb3 and phb4 for no reason Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> # Conflicts: # core/init.c # hw/phb3.c Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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