diff options
| author | Michael Neuling <mikey@neuling.org> | 2017-07-20 16:22:20 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-25 15:42:30 +1000 |
| commit | cf960e2884027b0b2f7bedd69b767a7ddceb960a (patch) | |
| tree | b7c622acb60575383b20f1252b55a3ef08f20bbb /include | |
| parent | 3530f67473652dfdbd14a94b07318e64f842297a (diff) | |
| download | talos-skiboot-cf960e2884027b0b2f7bedd69b767a7ddceb960a.tar.gz talos-skiboot-cf960e2884027b0b2f7bedd69b767a7ddceb960a.zip | |
phb4: Improve reset and link training timing
This improves PHB reset and link training timing. Justifications and
reasons are included in the patch.
Polling frequencies are decreased from 100ms to 10ms.
Added is a new state called PHB4_SLOT_LINK_STABLE which is now needed
since the link training can be so fast that we touch config space too
quickly (PCIe spec requires 1 second between PERST de-assert and
device config space reads). We use this new state to sanity check the
PHB and link before moving onto the PCI bus scan, where we no longer
recover from these error conditions.
Also added is simplified documentation of the PHB reset and training flow.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/pci-slot.h | 1 | ||||
| -rw-r--r-- | include/phb4.h | 6 |
2 files changed, 5 insertions, 2 deletions
diff --git a/include/pci-slot.h b/include/pci-slot.h index 479bc08c..5cc54f83 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -185,6 +185,7 @@ struct pci_slot { uint64_t delay_tgt_tb; uint64_t retries; uint64_t link_retries; + uint64_t stable_retries; struct pci_slot_ops ops; void *data; }; diff --git a/include/phb4.h b/include/phb4.h index 360889a5..b04e3f54 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -177,6 +177,7 @@ enum phb4_state { #define PHB4_SLOT_LINK_START (PHB4_SLOT_LINK + 1) #define PHB4_SLOT_LINK_WAIT_ELECTRICAL (PHB4_SLOT_LINK + 2) #define PHB4_SLOT_LINK_WAIT (PHB4_SLOT_LINK + 3) +#define PHB4_SLOT_LINK_STABLE (PHB4_SLOT_LINK + 4) #define PHB4_SLOT_HRESET PCI_SLOT_STATE_HRESET #define PHB4_SLOT_HRESET_START (PHB4_SLOT_HRESET + 1) #define PHB4_SLOT_HRESET_DELAY (PHB4_SLOT_HRESET + 2) @@ -213,9 +214,10 @@ struct phb4_err { uint32_t err_bit; }; -/* Link timeouts, increments of 100ms */ -#define PHB4_LINK_WAIT_RETRIES 20 +/* Link timeouts, increments of 10ms */ #define PHB4_LINK_ELECTRICAL_RETRIES 20 +#define PHB4_LINK_WAIT_RETRIES 200 +#define PHB4_LINK_STABLE_RETRIES 0 /* PHB4 flags */ #define PHB4_AIB_FENCED 0x00000001 |
