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* npu2: Use unfiltered mode in XTS tablesReza Arbab2018-03-122-44/+33
| | | | | | | | | | | | | | | | | | | | | | | | The XTS_PID context table is limited to 256 possible pids/contexts. To relieve this limitation, make use of "unfiltered mode" instead. If an entry in the XTS_BDF table has the bit for unfiltered mode set, we can just use one context for that entire bdf/lpar, regardless of pid. Instead of of searching the XTS_PID table, the NMMU checkout request will simply use the entry indexed by lparshort id instead. Change opal_npu_init_context() to create these lparshort-indexed wildcard entries (0-15) instead of allocating one for each pid. Check that multiple calls for the same bdf all specify the same msr value. In opal_npu_destroy_context(), continue validating the bdf argument, ensuring that it actually maps to an lpar, but no longer remove anything from the XTS_PID table. If/when we start supporting virtualized GPUs, we might consider actually removing these wildcard entries by keeping a refcount, but keep things simple for now. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Don't detect lock timeouts when timebase is invalidStewart Smith2018-03-091-0/+7
| | | | | | | | | | | | | | We can have threads waiting on hmi_lock who have an invalid timebase. Because of this, we want to go poke the register directly rather than rely on this_cpu()->tb_invalid (which won't have been set yet). Without this patch, you get something like this when you're injecting timebase errors: [10976.202052846,4] WARNING: Lock has been spinning for 10976394ms Fixes: 84186ef0944c9413262f0974ddab3fb1343ccfe8 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu_idle_job: relax a bitStewart Smith2018-03-081-0/+1
| | | | | | | | | This *dramatically* improves kernel boot time with GCOV builds from ~3minutes between loading kernel and switching the HILE bit down to around 10 seconds. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gcov: Another GCC, another gcov tweakStewart Smith2018-03-091-0/+4
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Keep constructors with prioritiesStewart Smith2018-03-081-1/+2
| | | | | | Fixes GCOV builds with gcc7, which uses this. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gcov: Add gcov data struct to sysfsMatt Brown2018-03-082-1/+4
| | | | | | | | | | | | Extracting the skiboot gcov data is currently a tedious process which involves taking a mem dump of skiboot and searching for the gcov_info struct. This patch adds the gcov struct to sysfs under /opal/exports. Allowing the data to be copied directly into userspace and processed. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> [stewart: refactor to dump out whole skiboot area, as gcov data is all over] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/lock: Add lock timeout warningsMatt Brown2018-03-071-0/+27
| | | | | | | | | | | | | | | | There are currently no timeout warnings for locks in skiboot. We assume that the lock will eventually become free, which may not always be the case. This patch adds timeout warnings for locks. Any lock which spins for more than 5 seconds will throw a warning and stacktrace for that thread. This is useful for debugging siturations where a lock which hang, waiting for the lock to be freed. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> [stewart: make code match comment, have 5s timeout] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/lock: Add deadlock detectionMatt Brown2018-03-073-1/+89
| | | | | | | | | | | | | This adds simple deadlock detection. The detection looks for circular dependencies in the lock requests. It will abort and display a stack trace when a deadlock occurs. The detection is enabled by DEBUG_LOCKS (enabled by default). While the detection may have a slight performance overhead, as there are not a huge number of locks in skiboot this overhead isn't significant. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> [stewart: fix build with DEBUG_LOCKS off] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Revert "console(lpc/fsp-console): Use only stdout-path property on P9 and above"Stewart Smith2018-03-064-35/+14
| | | | | | | | | | | | | This reverts commit 20f685a3627a2a522c465716377561a8fbcc608f. We've hit problems on Zaius machines and the needed petitboot changes haven't made it upstream yet. Let's revert for the time being while we sort everything out. We probably have to keep both around for a few years. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capp: Disable fast-reboot whenever enable_capi_mode() is calledVaibhav Jain2018-03-061-4/+2
| | | | | | | | | | | | | This patch updates phb4_set_capi_mode() to disable fast-reboot whenever enable_capi_mode() is called, irrespective to its return value. This should prevent against a possibility of not disabling fast-reboot when some changes to enable_capi_mode() causing return of an error and leaving CAPP in enabled mode. Suggested-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capp: Make error in capp timebase sync a non-fatal errorVaibhav Jain2018-03-061-3/+1
| | | | | | | | | | | | | | | | | | | | | | Presently when we encounter an error while synchronizing capp timebase with chip-tod at the end of enable_capi_mode() we return an error. This has an to unintended consequences. First this will prevent disabling of fast-reboot even though CAPP is already enabled by this point. Secondly, failure during timebase sync is a non fatal error or capp initialization as CAPP/PSL can continue working after this and an AFU will only see an error when it tries to read the timebase value from PSL. So this patch updates enable_capi_mode() to not return an error in case call to chiptod_capp_timebase_sync() fails. The function will now just log an error and continue further with capp init sequence. This make the current implementation align with the one in kernel 'cxl' driver which also assumes the PSL timebase sync errors as non-fatal init error. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-opencapi: Fix assert on link reset during initFrederic Barrat2018-03-061-0/+9
| | | | | | | | | | | | | | | | | | We don't support resetting an opencapi link yet. Commit fe6d86b9 ("pci: Make fast reboot creset PHBs in parallel") tries resetting any PHB whose slot defines a 'run_sm' callback. It raises an assert when applied to an opencapi PHB, as 'run_sm' calls the 'freset' callback, which is not yet defined for opencapi. Fix it for now by removing the currently useless definition of 'run_sm' on the opencapi slot. It will print a message in the skiboot log because the PHB cannot be reset, which is correct. It will all go away when we add support for resetting an opencapi link. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capp: Add lid definition for P9 DD-2.2Christophe Lombard2018-03-061-0/+2
| | | | | | | | | Update fsp_lid_map to include CAPP ucode lid for phb4-chipid == 0x202d1 that corresponds to P9 DD-2.2 chip. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Reduce log level of error messageMichael Neuling2018-03-061-1/+1
| | | | | | | | | | | | | | | | | If a link doesn't train, we can end up with error messages like this: [ 63.027261959,3] PHB#0032[8:2]: LINK: Timeout waiting for electrical link [ 63.027265573,3] PHB#0032:00:00.0 Error -6 resetting The first message is useful but the second message is just debug from the core PCI code and is confusing to print to the console. This reduces the second print to debug level so it's not seen by the console by default. Signed-off-by: Michael Neuling <mikey@neuling.org> Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot 5.10.2 release notesStewart Smith2018-03-061-0/+29
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit f14716595ee54cd3f55baaeae3c98bc16e7926b6) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Tie tm-suspend fw-feature and opal_reinit_cpus() togetherMichael Neuling2018-03-041-5/+22
| | | | | | | | | | | | | | | | | | | | | | | Currently opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) always returns OPAL_UNSUPPORTED. This ties the tm suspend fw-feature to the opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) so that when tm suspend is disabled, we correctly report it to the kernel. For backwards compatibility, it's assumed tm suspend is available if the fw-feature is not present. Currently hostboot will clear fw-feature(TM_SUSPEND_ENABLED) on P9N DD2.1. P9N DD2.2 will set fw-feature(TM_SUSPEND_ENABLED). DD2.0 and below has TM disabled completely (not just suspend). We are using opal_reinit_cpus() to determine this setting (rather than the device tree/HDAT) as some future firmware may let us change this dynamically after boot. That is not the case currently though. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fast-reboot: enable by default for POWER9Stewart Smith2018-03-011-5/+0
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Acked-By: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: set PBCQ Tunnel BAR for tunneled operationsPhilippe Bergheaud2018-03-015-6/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI tunneled operations (atomics and as_notify) that are initiated by devices. A subset of the tunneled operations require a response, that must be sent back from the host to the device. For example, an atomic compare and swap will return the compare status, as swap will only performed in case of success. Similarly, as_notify reports if the target thread has been woken up or not, because the operation may fail. To enable tunneled operations, a device driver must tell the host where it expects tunneled operation responses, by setting the PBCQ Tunnel BAR Response register with a specific value within the range of its BARs. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also operate in PCI mode, a new API is required to set the PBCQ Tunnel BAR Response register, without switching to CAPI mode. This patch provides two new OPAL calls to get/set the PBCQ Tunnel BAR Response register. Note: as there is only one PBCQ Tunnel BAR register, shared between all the devices connected to the same PHB, only one of these devices will be able to use tunneled operations, at any time. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: set PHB CMPM registers for tunneled operationsPhilippe Bergheaud2018-03-012-9/+44
| | | | | | | | | | | | | | | | | | | P9 supports PCI tunneled operations (atomics and as_notify) that require setting the PHB ASN Compare/Mask register with a 16-bit indication. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also work in PCI mode, the ASN Compare/Mask register should rather be initialized in phb4_init_ioda3(). This patch also adds "ibm,phb-indications" to the device tree, to tell Linux the values of CAPI, ASN, and NBW indications, when supported. Tunneled operations tested by IBM in CAPI mode, by Mellanox Technologies in PCI mode. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/hmi: report processor recovery reason from core FIR bits on P9Nicholas Piggin2018-03-011-3/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an error is encountered that causes processor recovery, HMI is generated if the recovery was successful. The reason is recorded in the core FIR, which gets copied into the WOF. In this case dump the WOF register and an error string into the OPAL msglog. A broken init setting led to HMIs reported in Linux as: [ 3.591547] Harmless Hypervisor Maintenance interrupt [Recovered] [ 3.591648] Error detail: Processor Recovery done [ 3.591714] HMER: 2040000000000000 This patch would have been useful because it tells us exactly that the problem is in the d-side ERAT: [ 414.489690798,7] HMI: Received HMI interrupt: HMER = 0x2040000000000000 [ 414.489693339,7] HMI: [Loc: UOPWR.0000000-Node0-Proc0]: P:0 C:1 T:1: Processor recovery occurred. [ 414.489699837,7] HMI: Core WOF = 0x0000000410000000 recovered error: [ 414.489701543,7] HMI: LSU - SRAM (DCACHE parity, etc) [ 414.489702341,7] HMI: LSU - ERAT multi hit In future it will be good to unify this reporting, so Linux could print something more useful. Until then, this gives some good data. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc/opal-api: Document changes of adding interrupt-parent property under ↵Pridhiviraj Paidipeddi2018-03-011-0/+2
| | | | | | | /ibm, opal/ipmi node on POWER9 and above. Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/ipmi-opal: Add interrupt-parent property for ipmi node on P9 and above.Pridhiviraj Paidipeddi2018-03-011-1/+7
| | | | | | | | | | | | | dtc complains below warning with newer 4.2+ kernels. dts: Warning (interrupts_property): Missing interrupt-parent for /ibm,opal/ipmi This fix adds interrupt-parent property under /ibm,opal/ipmi DT node on P9 and above, which allows ipmi-opal to properly use the OPAL irqchip. Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> [stewart: fix indentation] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc/opal-api: Document using stdout-path propertyPridhiviraj Paidipeddi2018-03-011-0/+1
| | | | | Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* console(lpc/fsp-console): Use only stdout-path property on P9 and abovePridhiviraj Paidipeddi2018-03-014-14/+35
| | | | | | | | | | | | | | | | | | | dtc tool complaining about below warning as usage of linux,stdout-path property under /chosen node is deprecated. dts: Warning (chosen_node_stdout_path): Use 'stdout-path' instead of 'linux,stdout-path' So this patch fix this by using stdout-path property on all the systems and keep linux,stdout-path only on P8 and before. This property refers to a node which represents the device to be used for boot console output. Verified boot on both P8 and P9 systems with new and older kernels. And also verified dtc warnings got fixed in both P8 and P9. Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> [stewart: simplify logic] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot.spec: Update to v5.10 releaseMurilo Opsfelder Araujo2018-03-011-3/+6
| | | | | | | Update skiboot.spec to be able to package skiboot v5.10 release. Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capp: Disable fast-reboot when capp is enabledVaibhav Jain2018-03-011-19/+19
| | | | | | | | | | | | | Ref[1] enables fast-reboot by default for POWER9. Presently fast-reboot for CAPP is not yet supported. Hence this patch disables fast-reboot in case the CAPP is enabled after reboot until its support is merged. References: [1] https://patchwork.ozlabs.org/patch/878879/ Suggested-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gitignore: Add *.aAndrew Donnellan2018-03-011-0/+1
| | | | | | | | | Since we're using thin archives now, we should ignore all the *.as lying around... Fixes: f6159cff5d91 ("build: use thin archives rather than incremental linking") Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc/device-tree: Add OpenCAPI device tree bindingsAndrew Donnellan2018-03-011-0/+69
| | | | | | Suggested-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc/device-tree: Add PCI bindings stubAndrew Donnellan2018-03-012-0/+73
| | | | | | | | | | Add a page for PCI device tree bindings. Right now it's just an example of a PHB as seen on a POWER9 Zaius, and it could do with some extra commentary. Suggested-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* platforms: Add OpenCAPI platform data and device tree nodesAndrew Donnellan2018-03-013-0/+119
| | | | | | | | | | | | | | | | Add OpenCAPI platform data for the zaius and zz platforms, as well as the generic platform that's used for BML boots. Currently, all three platforms are identical, but that won't always be the case (e.g. Witherspoon). Additionally, for Zaius, hardcode link information and the I2C bus that's required to reset OpenCAPI devices, because this currently can't be extracted from HDAT. Eventually this will go away once Hostboot adds the relevant data in HDAT. A later patch will add this for ZZ once we've done more testing. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-opencapi: Add OpenCAPI OPAL API callsFrederic Barrat2018-03-014-3/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add three OPAL API calls that are required by the ocxl driver. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The NPU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-opencapi: Train OpenCAPI links and setup devicesAndrew Donnellan2018-03-015-10/+746
| | | | | | | | | | | | | | | | | | | | | | | | Scan the OpenCAPI links under the NPU, and for each link, reset the card, set up a device, train the link and register a PHB. Implement the necessary operations for the OpenCAPI PHB type. For bringup, test and debug purposes, we allow an NVRAM setting, "opencapi-link-training" that can be set to either disable link training completely or to use the prbs31 test pattern. To disable link training: nvram -p ibm,skiboot --update-config opencapi-link-training=none To use prbs31: nvram -p ibm,skiboot --update-config opencapi-link-training=prbs31 Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-hw-procedures: Add support for OpenCAPI PHY link trainingAndrew Donnellan2018-03-013-12/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | Unlike NVLink, which uses the pci-virt framework to fake a PCI configuration space for NVLink devices, the OpenCAPI device model presents us with a real configuration space handled by the device over the OpenCAPI link. As a result, we have to train the OpenCAPI link in skiboot before we do PCI probing, so that config space can be accessed, rather than having link training being triggered by the Linux driver. Add some helper functions to wrap the existing NVLink PHY training sequence so we can easily run it within skiboot. Additionally, we add OpenCAPI-specific lane settings, and a function to "bump" lanes that haven't trained properly (this process isn't documented in the workbook, but the hardware experts assure us that this improves link training reliability...) We also support the PRBS31 pattern that's used for bringup and test purposes. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-opencapi: Configure NPU for OpenCAPIAndrew Donnellan2018-03-017-0/+927
| | | | | | | | | | | | | Scan the device tree for NPUs with OpenCAPI links and configure the NPU per the initialisation sequence in the NPU OpenCAPI workbook. Training of individual links and setup of per-AFU/link configuration will be in a later patch. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* platform: Add fields for OpenCAPI platform dataAndrew Donnellan2018-03-011-0/+14
| | | | | | | | | | Add a platform_ocapi struct to store platform-specific values for resetting OpenCAPI devices via I2C and for setting up the ODL PHY. A later patch will add this to the relevant platforms. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Rework NPU data structures for OpenCAPIAndrew Donnellan2018-03-014-84/+130
| | | | | | | | | | | | | | | | | | | | | Unlike NVLink, OpenCAPI registers a separate PHB for each device, in order to allow us to force Linux to use the correct MMIO windows for each NPU link. This requires some reworking of NPU data structures to account for the fact that a PHB could correspond to either an NPU (NVLink) or a single link (OpenCAPI). At some later point, we may want to rework the NVLink code to present a separate PHB per device in order to simplify this. For now, we split NVLink-specific device data into a separate struct in order to make it clear which fields are NVLink-only. Additionally, add helper functions to correctly translate between OpenCAPI/NVLink PHBs and the underlying structures, and various fields for OpenCAPI data that we're going to need later on. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Split out common helper functions into separate fileAndrew Donnellan2018-03-015-93/+122
| | | | | | | | | Split out common helper functions for NPU register access into a separate file, as these will be used extensively by both NVLink and OpenCAPI code. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc: skiboot 5.10.1 release notesStewart Smith2018-03-011-0/+23
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* README: document output filesJoel Stanley2018-02-281-0/+19
| | | | | | | | | | | | | A grumpy BMC developer was wondering which file to flash to the machines they were testing on. They longed for the old days where the answer was 'skiboot.lid'. Alas, those days are long past. This updates the readme with a list of the current output formats and where you might want to use them. Signed-off-by: Joel Stanley <joel@jms.id.au> [stewart: fix P8/P9 thing] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NPU2 HMIs: dump out a *LOT* of npu2 registers for debuggingStewart Smith2018-02-285-20/+69
| | | | | | | | | | This is not the way we want to end up doing this. This is a hack to make folk happy and not require crondump to debug nvidia/npu2 issues. Cc: stable Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/init: Assert when kernel not foundMichael Neuling2018-02-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the kernel doesn't load out of flash or there is nothing at KERNEL_LOAD_BASE, we end up with an esoteric message as we try to branch to out of skiboot into nothing [ 0.007197688,3] INIT: ELF header not found. Assuming raw binary. [ 0.014035267,5] INIT: Starting kernel at 0x0, fdt at 0x3044ad90 13029 [ 0.014042254,3] *********************************************** [ 0.014069947,3] Fatal Exception 0xe40 at 0000000000000000 [ 0.014085574,3] CFAR : 00000000300051c4 [ 0.014090118,3] SRR0 : 0000000000000000 SRR1 : 0000000000000000 [ 0.014096243,3] HSRR0: 0000000000000000 HSRR1: 9000000000001000 [ 0.014102546,3] DSISR: 00000000 DAR : 0000000000000000 [ 0.014108538,3] LR : 00000000300144c8 CTR : 0000000000000000 [ 0.014114756,3] CR : 40002202 XER : 00000000 [ 0.014120301,3] GPR00: 000000003001447c GPR16: 0000000000000000 This improves the message and asserts in this case: [ 0.014042685,5] INIT: Starting kernel at 0x0, fdt at 0x3044ad90 13049 bytes) [ 0.014049556,0] FATAL: Kernel is zeros, can't execute! [ 0.014054237,0] Assert fail: core/init.c:566:0 [ 0.014060472,0] Aborting! Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: Fix 'opal-runtime-size' propertyVasant Hegde2018-02-281-5/+5
| | | | | | | | | | | | | We are populating 'opal-runtime-size' before calculating actual stack size. Hence we endup having wrong runtime size (ex: on P9 it shows ~540MB while actual size is around ~40MB). Note that only device tree property is shows wrong value, but reserved-memory reflects correct size. init_all_cpus() calculates and updates actual stack size. Hence move this function call before add_opal_node(). Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fast-reboot: occ: Delete OCC child nodes in /ibm, opal/power-mgtShilpasri G Bhat2018-02-281-1/+5
| | | | | | | | | | | | Fast-reboot in P8 fails to re-init OCC data as there are chipwise OCC nodes which are already present in the /ibm,opal/power-mgt node. These per-chip nodes hold the voltage IDs for each pstate and these can be changed on OCC pstate table biasing. So delete these before calling the re-init code to re-parse and populate the pstate data. Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* build: use thin archives rather than incremental linkingNicholas Piggin2018-02-2830-35/+40
| | | | | | | | | | | | | | | | | | | | This changes to build system to use thin archives rather than incremental linking for built-in.o, similar to recent change to Linux. built-in.o is renamed to built-in.a, and is created as a thin archive with no index, for speed and size. All built-in.a are aggregated into a skiboot.tmp.a which is a thin archive built with an index, making it suitable or linking. This is input into the final link. The advantags of build size and linker code placement flexibility are not as great with skiboot as a bigger project like Linux, but it's a conceptually better way to build, and is more compatible with link time optimisation in toolchains which might be interesting for skiboot particularly for size reductions. Size of build tree before this patch is 34.4MB, afterwards 23.1MB. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Add fw-feature flags for security related settingsMichael Ellerman2018-02-281-1/+22
| | | | | | | | | | | | | | | | | | | Newer firmwares report some feature flags related to security settings via HDAT. On real hardware skiboot translates these into device tree properties. For testing purposes just create the properties manually in the tcl. These values don't exactly match any actual chip revision, but the code should not rely on any exact set of values anyway. We just define the most interesting flags, that if toggled to "disable" will change Linux behaviour. You can see the actual values in the hostboot source in src/usr/hdat/hdatiplparms.H. Also add an environment variable for easily toggling the top-level "security on" setting. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* direct-controls: mambo fix for multiple chipsNicholas Piggin2018-02-281-2/+8
| | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Make fast reboot creset PHBs in parallelMichael Neuling2018-02-281-30/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In this patch, we added a creset to the fast reboot path: commit a1eba9d29d17ff44fca1293b071023a9fbf4b938 Author: Andrew Donnellan <andrew.donnellan@au1.ibm.com> fast-reboot: creset PHBs on fast reboot Unfortunately, this does the creset in serial rather than in parallel. This patch changes the creset on fast reboot to operate in parallel. It simplifies the code by abstracting pci_init_slots() so that it can be used on boot and fast reboot to perform all the PCI retraining. This improves fast reboot PCI training on a dual chip P9 from ~12 seconds down to ~2 seconds. Similar improvements for P8 are achieved as well. This means the time to download the BOOTKERNEL is the bottleneck for fast reboot. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Russell Currey <ruscur@russell.cc> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Move code aroundMichael Neuling2018-02-281-63/+63
| | | | | | | | | | | This just moves some functions around. A future patch will reuse some of these in different locations, so the order needs to change. No code or functional changes Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libflash/blocklevel: Correct miscalculation in blocklevel_smart_erase()Cyril Bur2018-02-281-1/+1
| | | | | | | | | | | | | | If blocklevel_smart_erase() detects that the smart erase fits entire in one erase block, it has an early bail path. In this path it miscaculates where in the buffer the backend needs to read from to perform the final write. Fixes: d6a5b53f ("libflash/blocklevel: Add blocklevel_smart_erase()") Fixes: https://github.com/open-power/skiboot/issues/151 Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libstb/secureboot: Fix logging of secure verify messages.Pridhiviraj Paidipeddi2018-02-281-12/+19
| | | | | | | | | Currently we are logging secure verify/enforce messages in PR_EMERG level even when there is no secureboot mode enabled. So reduce the log level to PR_ERR when secureboot mode is OFF. Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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