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* make_version: Fix check for '.version' fileVaibhav Jain2017-11-211-1/+1
| | | | | | | | | | | | | | | | | | | When building from the non-git tree and with '.version' file missing, make_version shows this bash error message. % make ... cat: .version: No such file or directory ... error You need to set SKIBOOT_VERSION environment variable This patch fixes this issue by updating '.version' file check in make_version script to test if it exists as a regular file and is of non-zero size. Fixes: 6a3cad272e4c("Add fallback to .version if not git and no SKIBOOT_VERSION") Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* external/pflash: Fix erasing within a single erase blockCyril Bur2017-11-203-10/+14
| | | | | | | | | | | | | | It is possible to erase within a single erase block. Currently the pflash code assumes that if the erase starts part way into an erase block it is because it needs to be aligned up to the boundary with the next erase block. Doing an erase smaller than a single erase block will cause underflows and looping forever on erase. Fixes: ae6cb86c2 ("external/pflash: Reinstate the progress bars") Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/dts: retry special wakeup operation if core still gatedRobert Lippert2017-11-201-1/+29
| | | | | | | | | | | | | It has been observed that in some cases the special wakeup operation can "succeed" but the core is still in a gated/offline state. Check for this state after attempting to wakeup a core and retry the wakeup if necessary. Change-Id: Ia6b1b75dcab590c299bed3ee0a42031f09c39eda Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/direct-controls: add function to read core gated stateRobert Lippert2017-11-202-0/+22
| | | | | | Change-Id: Ib534503f2528de4d8b1633d9859ae9ff5d010f98 Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/direct-controls: wait for core special wkup bit clearedRobert Lippert2017-11-201-1/+22
| | | | | | | | | | | | | | | When clearing special wakeup bit on a core, wait until the bit is actually cleared by the hardware in the status register until returning success. This may help avoid issues with back-to-back reads where the special wakeup request is cleared but the firmware is still processing the request and the next attempt to set the bit reads an immediate success from the previous operation. Change-Id: I86ec8cbbbddd1a5724f451244907693bc09e01ea Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: dts: Assert special wakeup on idle cores while reading temperatureShilpasri G Bhat2017-11-205-17/+79
| | | | | | | | | | | | In P9, when a core enters a stop state, its clocks will be stopped to save power and hence we will not be able to perform a scom operation to read the DTS temperature sensor. Hence, assert a special wakeup on cores that have entered a stop state in order to successfully complete the scom operation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [rlippert@google.com: Clear special wakeup only when it succeeds] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* OCC: Increase max pstate check on P9 to 255Stewart Smith2017-11-201-4/+6
| | | | | | | | | | | | This has changed from P8, we can now have > 127 pstates. This was observed on Boston during WoF bringup. Reported-by: Minda Wei <minda.wei@ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Reported-by: Francesco A Campisano <campisan@us.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libpore: Fix incorrect mtspr instruction generationCyril Bur2017-11-201-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | >From coverity defect 173758: CID 173758 (#1 of 1): Unused value (UNUSED_VALUE) assigned_value: Assigning value from (uint8_t)i_Rs << 21 to mtsprInstOpcode here, but that stored value is overwritten before it can be used. This causes the generated mtspr to always move from register r0 as opposed to the function parameter i_Rs. Luckily the only call to getMtsprInstruction is: getMtsprInstruction( 0, (uint16_t)i_regId ); the first parameter is the register so in an incredible stroke of luck, the requirement is to generate a mtspr from r0. Therefore no bug exists today, this is still a fairly important fix because if anyone uses getMtsprInstruction() with a non zero first parameter, it will cause them endless headache. Fixes: CID 173758 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* p8-i2c: Limit number of retry attemptsOliver O'Halloran2017-11-202-2/+11
| | | | | | | | | | | | Current we will attempt to start an I2C transaction until it succeeds. In the event that the OCC does not release the lock on an I2C bus this results in an async token being held forever and the kernel thread that started the transaction will block forever while waiting for an async completion message. Fix this by limiting the number of attempts to start the transaction. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Add OpenBMC vPNOR supportOliver O'Halloran2017-11-201-0/+31
| | | | | | | | | A big-ol-hack to add some checking for OpenBMC's vPNOR GUARD files under /media/pnor-prsv. This isn't ideal since it doesn't handle the create case well, but it's better than nothing. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Always use MTD to access flashOliver O'Halloran2017-11-201-0/+8
| | | | | | | | | Direct mode is generally either unsafe or unsupported. We should always access the PNOR via an MTD device so make that the default. If someone really needs direct mode, then they can use pflash. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libflash: Fix parity calculation on ARMOliver O'Halloran2017-11-201-1/+1
| | | | | | | | | | | To calculate the ECC syndrome we need to calculate the parity of a 64bit number. On non-powerpc platforms we use the gcc builtin function __builtin_parityl() to do this calculation. This is broken on 32bit ARM where sizeof(unsigned long) is four bytes. Using __builtin_parityll() instead cures this. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: create: Allow creating arbitrary GARD recordsOliver O'Halloran2017-11-202-4/+76
| | | | | | | | | | | | | | | | | | | | | Add a new sub-command that allows us to create GARD records for arbitrary chip units. There isn't a whole lot of constraints on this and that limits how useful it can be, but it does allow a user to GARD out individual DIMMs, chips or cores from the BMC (or host) if needed. There are a few caveats though: 1) Not everything can, or should, have a GARD record applied it to. 2) There is no validation that the unit actually exists. Doing that sort of validation requires something that understands the FAPI targeting information (I think) and adding support for it here would require some knowledge from the system XML file. 3) There's no way to get a list of paths in the system. 4) Although we can create a GARD record at runtime it won't be applied until the next IPL. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Add path parsing supportOliver O'Halloran2017-11-201-0/+87
| | | | | | | | In order to support manual GARD records we need to be able to parse the hardware unit path strings. This patch implements that. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: list: Improve outputOliver O'Halloran2017-11-202-25/+68
| | | | | | | | | Display the full aath to the GARDed hardware unit in each record rather than relying on the output of `gard show` and convert do_list() to use the iterator while we're here. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: {list, show}: Fix the Type field in the outputOliver O'Halloran2017-11-204-3/+49
| | | | | | | | | | | The output of `gard list` has a field named "Type", however this doesn't actually indicate the type of the record. Rather, it shows the type of the path used to identify the hardware being GARDed. This is of pretty dubious value considering the Physical path seems to always be used when referring to GARDed hardware. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Use iterators for count_record()Oliver O'Halloran2017-11-201-41/+12
| | | | | | | | Starting coverting code to use the iterators and fix some bad naming along the way. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Add iteratorsOliver O'Halloran2017-11-201-0/+31
| | | | | | | | | Add a `for_each_gard` iterator rather than using do_iterate. Callbacks are banned under the Genoa convention and we need to apply a zero-tolerance policy. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Replace is_valid_id with is_valid_record()Oliver O'Halloran2017-11-201-4/+4
| | | | | | | It was annoying me. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Add P9 supportOliver O'Halloran2017-11-206-2/+46
| | | | | Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: Update chip unit dataOliver O'Halloran2017-11-205-121/+187
| | | | | | | | | | | | Source the list of units from the hostboot source rather than the previous hard coded list. The list of path element types changes between generations so we need to add a level of indirection to accommodate P9. This also changes the names used to match those printed by Hostboot at IPL time and paves the way to adding support for manual GARD record creation. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gard: show: Remove "Res Recovery" fieldOliver O'Halloran2017-11-202-2/+0
| | | | | | | | This field has never been populated by hostboot on OpenPower systems so there's no real point in reporting it's contents. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Remove unused npu2_dev struct membersAndrew Donnellan2017-11-191-3/+0
| | | | | | | | | | | | There's a few members of struct npu2_dev that are completely unused. Remove them. Cc: Alistair Popple <alistair@popple.id.au> Cc: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdata/vpd: add support for parsing CPU VRML recordsRobert Lippert2017-11-191-0/+24
| | | | | | | | | Allows skiboot to parse out the processor part/serial numbers on OpenPOWER P9 machines. Change-Id: Ie22a3c50d32f480671334b4b6c820476e29301c9 Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot 5.9.2 release notesStewart Smith2017-11-161-0/+80
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit f37f867949a8b17f7d33dd6c967282f50ae9ef52) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix lane equalisation settingMichael Neuling2017-11-151-1/+1
| | | | | | | | | | | Fix cut and paste from phb3. The sizes have changes now we have GEN4, so the check here needs to change also Without this we end up with the default settings (all '7') rather than what's in HDAT. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hdata: Fix copying GEN4 lane equalisation settingsMichael Neuling2017-11-151-0/+2
| | | | | | | These aren't copied currently but should be. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix PE mapping of M32 BARBenjamin Herrenschmidt2017-11-151-13/+11
| | | | | | | | | | | | | The M32 BAR is the PHB4 region used to map all the non-prefetchable or 32-bit device BARs. It's supposed to have its segments remapped via the MDT and Linux relies on that to assign them individual PE#. However, we weren't configuring that properly and instead used the mode where PE# == segment#, thus causing EEH to freeze the wrong device or PE#. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Fix lost bit in PE number on config accessesBenjamin Herrenschmidt2017-11-151-3/+3
| | | | | | | | | | A PE number can be up to 9 bits, using a uint8_t won't fly.. That was causing error on config accesses to freeze the wrong PE. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Revert "npu2: hw-procedures: Enable low power mode"Reza Arbab2017-11-152-24/+1
| | | | | | | | | | | As it turns out, low power mode is not yet ready for prime time. We shouldn't write the low power config register until it is. This reverts commit a05054c53a37850a2118d01fcf6669ebb10d1a33. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Move to new GPU memory mapMichael Neuling2017-11-155-5/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three different ways we configure the MCD and memory map. 1) Old way (current way) Skiboot configures the MCD and puts GPUs at 4TB and below 2) New way with MCD Hostboot configures the MCD and skiboot puts GPU at 4TB and above 3) New way without MCD No one configures the MCD and skiboot puts GPU at 4TB and below The patch keeps option 1 and adds options 2 and 3. The different configurations are detected using certain scoms (see patch). Option 1 will go away eventually as it's a configuration that can cause xstops or data integrity problems. We are keeping it around to support existing hostboot. Option 2 supports only 4 GPUs and 512GB of memory per socket. Option 3 supports 6 GPUs and 4TB of memory but may have some performance impact. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phys-map: Rename GPU_MEM to GPU_MEM_4T_DOWNMichael Neuling2017-11-153-12/+12
| | | | | | | | | | | This map is soon to be replaced, but we are going to keep it around for a little while so that we support older hostboot firmware. Rename it for now. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: MCD refactorMichael Neuling2017-11-151-13/+20
| | | | | | | | | | Pull out MCD writing code into npu2_mcd_init() No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Refactor BAR setting codeMichael Neuling2017-11-152-6/+8
| | | | | | | | | | | | | | | | | This refactors the BAR setting code to make it clearer and handle a larger range of BAR addresses. This is needed as we are about to move the GPU to a physical address that is currently not supported by this code. This change derives group and chip sections of the BAR from the base address rather than the chip_id now. mem sel is also derived from the base address, rather than assuming 0. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Create npu2_write_mcd()Michael Neuling2017-11-152-8/+19
| | | | | | | | | This code is replicated, so let's put it in a function. Also add some cleanups. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-prd: flush after logging to stdio in debug modeJeremy Kerr2017-11-131-0/+3
| | | | | | | | When in debug mode, flush after each log output. This makes it more likely that we'll catch failure reasons on severe errors. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Remove side effects in assert() calls.Cyril Bur2017-11-131-3/+7
| | | | | | | | | | | | | | | This likely looks intentional and will do the correct thing. The correct behaviour does rely on the fact that skiboot has a custom assert() which will always generate code. 'Regular' assert() can be made to generate no code. If we were to do that with this code, the results would be, interesting! This patch will also keep Coverity happy which is nice. Fixes: CID 145242, 172044 and 172045 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pcie-slots: Fix coverity possible NULL dereferenceCyril Bur2017-11-131-2/+3
| | | | | | | | | | | Coverity has found a senario where there could be a NULL dereference, it is likely that in practice we wouldn't hit this. Coverity does point out that all other callers of pcie_slot_create() do check for the NULL return, as such it makes sense to add a check. Fixes: CID 173756 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* p8-i2c: Don't write the watermark register at initOliver O'Halloran2017-11-131-12/+8
| | | | | | | | | | | | | | | | On P9 the I2C master is shared with the OCC. Currently the watermark values are set once at init time which is bad for two reasons: a) We don't take the OCC master lock before setting it. Which may cause issues if the OCC is currently using the master. b) The OCC might change the watermark levels and we need to reset them. Change this so that we set the watermark value when a new transaction is started rather than at init time. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Update initsMichael Neuling2017-11-131-1/+1
| | | | | | | | | | New init value from HW folks for the fence enable register. This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error) Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* doc: Fix reference to overview in READMERussell Currey2017-11-131-1/+1
| | | | | Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot 5.9.1 release notesStewart Smith2017-11-141-0/+29
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 46c41629bb43ec894fc1dc20502b252e15c24818) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: hw-procedures: Refactor reset_ntl procedureReza Arbab2017-11-131-15/+58
| | | | | | | | | | Change the implementation of reset_ntl to match the latest programming guide documentation. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: hw-procedures: Add phy_rx_clock_sel()Reza Arbab2017-11-132-1/+20
| | | | | | | | | Change the RX clk mux control to be done by software instead of HW. This avoids glitches caused by changing the mux setting. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2: Add npu2_write_mask_4b()Reza Arbab2017-11-132-0/+12
| | | | | | | | | Add a 4-byte version of npu2_write_mask(). Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ffspart/pflash: fix tests for new VOLATILE flagStewart Smith2017-11-106-22/+27
| | | | | Fixes: b786e7ba1d34c5a4d8baa6304f4d930539cefac8 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Document fsp-ipl-params to sp-ipl-paramsStewart Smith2017-11-101-1/+1
| | | | | Fixes: eb858339cae8240367c82e6c2cc139519dbddb26 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pflash: Support for volatile flagAdriana Kobylak2017-11-098-12/+32
| | | | | | | | | The volatile flag was added to the pnor image to indicate partitions that are cleared during a host power off. Display this flag from the pflash command. Signed-off-by: Adriana Kobylak <anoo@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm/head: Loop after attnOliver O'Halloran2017-11-091-0/+1
| | | | | | | | | | We use the attn instruction to raise an error in early boot if OPAL don't recognise the PVR. It's possible for hostboot to disable the attn instruction before entering OPAL so add an extra busy loop after the attn to prevent attempting to boot on an unknown processor. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Trivial fix for compilation error when enabling xive debugGuilherme G. Piccoli2017-11-091-1/+1
| | | | | | | | | | | Without this, we get: hw/xive.c: In function ‘xive_special_cache_check’: hw/xive.c:2982:9: error: missing initializer for field ‘w0’ of ‘struct xive_vp’ [-Werror=missing-field-initializers] Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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