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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2015-04-09 15:08:28 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-04-15 05:40:18 +1000 |
| commit | cf99c29e04f60f5430c9a7d32cb283cd10aaa38c (patch) | |
| tree | 836d5a5ef9da774c416114fcc8f8a8b3fbda8549 /include/phb3-regs.h | |
| parent | fb824365808a2b2a55c141c512306652eb4707c5 (diff) | |
| download | talos-skiboot-cf99c29e04f60f5430c9a7d32cb283cd10aaa38c.tar.gz talos-skiboot-cf99c29e04f60f5430c9a7d32cb283cd10aaa38c.zip | |
phb3: Add Naples PHB support
This detects the new PHB revision and does the appropriate updates
to the init sequence.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3-regs.h')
| -rw-r--r-- | include/phb3-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb3-regs.h b/include/phb3-regs.h index b3f71601..632ed93e 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -169,6 +169,8 @@ /* PCI-E Stack registers */ #define PHB_PCIE_SYSTEM_CONFIG 0x600 +#define PHB_PCIE_SCONF_SLOT PPC_BIT(15) +#define PHB_PCIE_SCONF_MAXLINKSPEED PPC_BITMASK(32,35) #define PHB_PCIE_BUS_NUMBER 0x608 #define PHB_PCIE_SYSTEM_TEST 0x618 #define PHB_PCIE_LINK_MANAGEMENT 0x630 |
