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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-07-06 12:09:52 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-12-08 11:34:20 +1100 |
| commit | aed1fbe848ec7dcfef5c2831ab779ae9c21b41f6 (patch) | |
| tree | 55bd5326c2fc4bbe66627812c96a3f7091bbeb9a /include/phb3-regs.h | |
| parent | 95edf12c0872ef59475d6d2afc64865d2e923b71 (diff) | |
| download | talos-skiboot-aed1fbe848ec7dcfef5c2831ab779ae9c21b41f6.tar.gz talos-skiboot-aed1fbe848ec7dcfef5c2831ab779ae9c21b41f6.zip | |
phb3: Trick to allow control of the PCIe link width and speed
This implements a hook inside OPAL that catches 16 and 32 bit writes
to the link status register of the PHB.
It allows you to write a new speed or a new width, and OPAL will then
cause the PHB to renegociate.
Example:
First read the link status on PHB4:
setpci -s 0004:00:00.0 0x5a.w
a103
It's at x16 Gen3 speed (8GT/s)
bits 0x0ff0 are the width and 0x000f the speed. The width can be
1 to 16 and the speed 1 to 3 (2.5, 5 and 8GT/s)
Then try to bring it down to 1x Gen1 :
setpci -s 0004:00:00.0 0x5a.w=0xa011
Observe the result in the PHB:
/ # lspci -s 0004:00:00.0 -vv
0004:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode])
.../...
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+
And in the device:
/ # lspci -s 0004:01:00.0 -vv
.../...
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3-regs.h')
| -rw-r--r-- | include/phb3-regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/phb3-regs.h b/include/phb3-regs.h index 91f25f98..5a3cea60 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -175,7 +175,12 @@ #define PHB_PCIE_BUS_NUMBER 0x608 #define PHB_PCIE_SYSTEM_TEST 0x618 #define PHB_PCIE_LINK_MANAGEMENT 0x630 +#define PHB_PCIE_LM_CHG_LINK_WIDTH PPC_BIT(0) +#define PHB_PCIE_LM_TGT_LINK_WIDTH PPC_BITMASK(2,7) #define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8) +#define PHB_PCIE_LM_DL_WCHG_PENDING PPC_BIT(9) +#define PHB_PCIE_LM_CHG_SPEED PPC_BIT(11) +#define PHB_PCIE_LM_TGT_SPEED PPC_BITMASK(12,15) #define PHB_PCIE_DLP_TRAIN_CTL 0x640 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1) #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16) |
