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authorGavin Shan <gwshan@linux.vnet.ibm.com>2014-10-02 16:30:12 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-10-08 14:07:46 +1100
commit666ee3d06824400eff61c30d7722ea60d673fe8c (patch)
tree29b9cabdea0858ffad3d1b7f268382969649a177 /include/phb3-regs.h
parent4bb318eeeb67d40071020de87dedbf5a04538b48 (diff)
downloadtalos-skiboot-666ee3d06824400eff61c30d7722ea60d673fe8c.tar.gz
talos-skiboot-666ee3d06824400eff61c30d7722ea60d673fe8c.zip
PHB3: Support multiple MM32 segments for error injection
When doing error injection to 32-bits MMIO range, fixed length 8MB is used. That's incorrect as one PE might span multile segments. Also the 32-bits MMIO segment size isn't 8MB necessarily. The patch fixes the issue to cover all (contiguous) 32-bits MMIO segments assigned to the specified PE. Also, it fixes the 48 bits of 50 bits AIB address, instead of all bits used for comparison. BZ: 115222 Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include/phb3-regs.h')
-rw-r--r--include/phb3-regs.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/phb3-regs.h b/include/phb3-regs.h
index 2611b5f9..686a1136 100644
--- a/include/phb3-regs.h
+++ b/include/phb3-regs.h
@@ -144,11 +144,13 @@
#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
#define PHB_PAPR_ERR_INJ_ADDR 0x2b8
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16,63)
+#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63)
#define PHB_PAPR_ERR_INJ_MASK 0x2c0
#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11)
#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11)
-#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(14,40) /* 8M aligned */
-#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(40)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,63)
+#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63)
#define PHB_ETU_ERR_SUMMARY 0x2c8
/* UTL registers */
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