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| author | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-05-07 18:19:16 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-05-15 07:59:19 +1000 |
| commit | d3bd6d6c48446d5290c39b78a93c5b8aae91b369 (patch) | |
| tree | 976582798cdec3c928b0fdcb2ed743102cccf0a5 | |
| parent | 449fa1606c08583c50db8766b581299777c39c83 (diff) | |
| download | talos-skiboot-d3bd6d6c48446d5290c39b78a93c5b8aae91b369.tar.gz talos-skiboot-d3bd6d6c48446d5290c39b78a93c5b8aae91b369.zip | |
Add 2MB to skiboot heap
Rearrange memory map slightly, adding in an extra 2MB into skiboot
heap.
We lost 1MB of HEAP when allowing skiboot binary to be 2MB, and we
were starting to get close to not having a lot of room to play
with, especially on larger systems.
With this patch:
- on Tuleta, we now have 4,422,472 free in firmware-heap for runtime.
- on Mambo, we have 13,094,080 free
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | include/mem-map.h | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/include/mem-map.h b/include/mem-map.h index 2a903d13..1258d87d 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -65,16 +65,12 @@ * * As of this writing (2014/4/6), we use approc 512K for skiboot * core and 2M of heap on a 1 socket machine. + * + * As of 2015/5/7 we use approx 800k for skiboot, 500k HEAP for + * mambo boot. */ #define HEAP_BASE (SKIBOOT_BASE + 0x00300000) -#define HEAP_SIZE 0x00b00000 - -/* This is our PSI TCE table. It's 16K entries on P7 and 256K - * entries on P8 - */ -#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x00e00000) -#define PSI_TCE_TABLE_SIZE_P7 0x00020000UL -#define PSI_TCE_TABLE_SIZE_P8 0x00200000UL +#define HEAP_SIZE 0x00d00000 /* This is the location of our console buffer at base + 16M */ #define INMEM_CON_START (SKIBOOT_BASE + 0x01000000) @@ -88,11 +84,18 @@ #define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000) #define SPIRA_HEAP_SIZE 0x00800000 +/* This is our PSI TCE table. It's 16K entries on P7 and 256K + * entries on P8 + */ +#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) +#define PSI_TCE_TABLE_SIZE_P7 0x00020000UL +#define PSI_TCE_TABLE_SIZE_P8 0x00200000UL + /* Total size of the above area * * (Ensure this has at least a 64k alignment) */ -#define SKIBOOT_SIZE 0x01a00000 +#define SKIBOOT_SIZE 0x01c00000 /* We start laying out the CPU stacks from here, indexed by PIR * each stack is STACK_SIZE in size (naturally aligned power of |
