phb*: Remove the state field in the various phb structures

We've been carting around this field since the original p7ioc-phb code.
As far as I can tell we never actually use it for anything other than
checking if the PHB has been marked as broken or not. The _FENCED
state is set in a few places, but we never use it in favour of just
checking the MMIO register.

This patch just replaces it with a boolean that indicates if
the PHB has been marked as broken and removes the giant, mostly
wrong, comment explaining it's usage that is copied and pasted
into each phb header file.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

7 files changed, 40 insertions, 233 deletions

diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index b0a26e84..fafd841e 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -76,7 +76,7 @@ static int64_t p7ioc_pcicfg_check(struct p7ioc_phb *p, uint32_t bdfn,
 		return OPAL_HARDWARE;
 
 	/* Check PHB state */
-	if (p->state == P7IOC_PHB_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	return OPAL_SUCCESS;
@@ -296,7 +296,7 @@ static int64_t p7ioc_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 	*pci_error_type = OPAL_EEH_NO_ERROR;
 
 	/* Check dead */
-	if (p->state == P7IOC_PHB_STATE_BROKEN) {
+	if (p->broken) {
 		*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		if (severity)
@@ -311,7 +311,6 @@ static int64_t p7ioc_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		if (severity)
 			*severity = OPAL_EEH_SEV_PHB_FENCED;
-		p->state = P7IOC_PHB_STATE_FENCED;
 		goto bail;
 	}
 
@@ -372,7 +371,7 @@ static int64_t p7ioc_eeh_next_error(struct phb *phb, uint64_t *first_frozen_pe,
 	*first_frozen_pe = (uint64_t)-1;
 
 	/* Check dead */
-	if (p->state == P7IOC_PHB_STATE_BROKEN) {
+	if (p->broken) {
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		*severity = OPAL_EEH_SEV_PHB_DEAD;
 		return OPAL_SUCCESS;
@@ -383,7 +382,6 @@ static int64_t p7ioc_eeh_next_error(struct phb *phb, uint64_t *first_frozen_pe,
 		/* Should be OPAL_EEH_STOPPED_TEMP_UNAVAIL ? */
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		*severity = OPAL_EEH_SEV_PHB_FENCED;
-		p->state = P7IOC_PHB_STATE_FENCED;
 		p7ioc_phb_set_err_pending(p, false);
 		return OPAL_SUCCESS;
 	}
@@ -2474,7 +2472,7 @@ static void p7ioc_phb_err_interrupt(struct irq_source *is, uint32_t isn)
 	opal_pci_eeh_set_evt(p->phb.opal_id);
 
 	/* If the PHB is broken, go away */
-	if (p->state == P7IOC_PHB_STATE_BROKEN)
+	if (p->broken)
 		return;
 
 	/*
@@ -2483,7 +2481,6 @@ static void p7ioc_phb_err_interrupt(struct irq_source *is, uint32_t isn)
 	 */
 	phb_lock(&p->phb);
 	if (p7ioc_phb_fenced(p)) {
-		p->state = P7IOC_PHB_STATE_FENCED;
 		PHBERR(p, "ER error ignored, PHB fenced\n");
 		phb_unlock(&p->phb);
 		return;
@@ -2657,7 +2654,6 @@ void p7ioc_phb_setup(struct p7ioc *ioc, uint8_t index)
 	p->io_base = ioc->mmio1_win_start + PHBn_IO_BASE(index);
 	p->m32_base = ioc->mmio2_win_start + PHBn_M32_BASE(index);
 	p->m64_base = ioc->mmio2_win_start + PHBn_M64_BASE(index);
-	p->state = P7IOC_PHB_STATE_UNINITIALIZED;
 	p->phb.scan_map = 0x1; /* Only device 0 to scan */
 
 	/* Find P7IOC base location code in IOC */
@@ -2959,7 +2955,11 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
 
 	PHBDBG(p, "Initializing PHB %x...\n", p->index);
 
-	p->state = P7IOC_PHB_STATE_INITIALIZING;
+	/*
+	 * We re-init the PHB on a creset (and a few other cases)
+	 * so clear the broken flag
+	 */
+	p->broken = false;
 
 	/* For some reason, the doc wants us to read the version
 	 * register, so let's do it. We shoud probably check that
@@ -3173,14 +3173,11 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
 	out_be64(p->regs + PHB_TIMEOUT_CTRL1,		   0x1611112010200000UL);
 	out_be64(p->regs + PHB_TIMEOUT_CTRL2,		   0x0000561300000000UL);
 
-	/* Mark the PHB as functional which enables all the various sequences */
-	p->state = P7IOC_PHB_STATE_FUNCTIONAL;
-
 	return OPAL_SUCCESS;
 
  failed:
 	PHBERR(p, "Initialization failed\n");
-	p->state = P7IOC_PHB_STATE_BROKEN;
+	p->broken = true;
 
 	return OPAL_HARDWARE;
 }
@@ -3206,7 +3203,7 @@ void p7ioc_phb_reset(struct phb *phb)
 	 * notable that the IODA table cache won't be emptied so that we
 	 * can restore them during error recovery.
 	 */
-	if (p->state == P7IOC_PHB_STATE_FUNCTIONAL && !fenced) {
+	if (!p->broken && !fenced) {
 		PHBDBG(p, "  ioda reset ...\n");
 		p7ioc_ioda_reset(&p->phb, false);
 		time_wait_ms(100);
@@ -3247,7 +3244,7 @@ void p7ioc_phb_reset(struct phb *phb)
 	/* Reset failed, not much to do, maybe add an error return */
 	if (fenced) {
 		PHBERR(p, "Reset failed, fence still set !\n");
-		p->state = P7IOC_PHB_STATE_BROKEN;
+		p->broken = true;
 		return;
 	}
 
diff --git a/hw/p7ioc.c b/hw/p7ioc.c
index fc035d6b..e036433a 100644
--- a/hw/p7ioc.c
+++ b/hw/p7ioc.c
@@ -666,8 +666,6 @@ static void p7ioc_create_hub(struct dt_node *np)
 	for (i = 0; i < P7IOC_NUM_PHBS; i++) {
 		if (p7ioc_phb_enabled(ioc, i))
 			p7ioc_phb_setup(ioc, i);
-		else
-			ioc->phbs[i].state = P7IOC_PHB_STATE_OFF;
 	}
 
 	/* Now, we do the bulk of the inits */
diff --git a/hw/phb3.c b/hw/phb3.c
index 0c4e1eb3..f28f568f 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -72,7 +72,6 @@ static bool phb3_fenced(struct phb3 *p)
 	xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir);
 	if (nfir & PPC_BIT(16)) {
 		p->flags |= PHB3_AIB_FENCED;
-		p->state = PHB3_STATE_FENCED;
 		return true;
 	}
 	return false;
@@ -134,7 +133,7 @@ static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn,
 		return OPAL_HARDWARE;
 
 	/* Check PHB state */
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/* Fetch the PE# from cache */
@@ -1798,7 +1797,7 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn,
 	index = p8_irq_to_phb(isn);
 	ive_num = PHB3_IRQ_NUM(isn);
 
-	if (p->state == PHB3_STATE_BROKEN || !p->tbl_rtt)
+	if (p->broken || !p->tbl_rtt)
 		return OPAL_HARDWARE;
 	if (chip != p->chip_id ||
 	    index != p->index ||
@@ -1908,7 +1907,7 @@ static int64_t phb3_lsi_set_xive(struct irq_source *is, uint32_t isn,
 	index = p8_irq_to_phb(isn);
 	irq = PHB3_IRQ_NUM(isn);
 
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	if (chip != p->chip_id	||
@@ -1953,7 +1952,7 @@ static void phb3_err_interrupt(struct irq_source *is, uint32_t isn)
 				OPAL_EVENT_PCI_ERROR);
 
 	/* If the PHB is broken, go away */
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return;
 
 	/*
@@ -2181,7 +2180,7 @@ static int64_t phb3_get_presence_state(struct pci_slot *slot, uint8_t *val)
 	struct phb3 *p = phb_to_phb3(slot->phb);
 	uint64_t hp_override;
 
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/*
@@ -2675,7 +2674,6 @@ static int64_t phb3_creset(struct pci_slot *slot)
 	}
 
 error:
-	p->state = PHB3_STATE_FENCED;
 	return OPAL_HARDWARE;
 }
 
@@ -2732,7 +2730,7 @@ static int64_t phb3_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 	*pci_error_type = OPAL_EEH_NO_ERROR;
 
 	/* Check dead */
-	if (p->state == PHB3_STATE_BROKEN) {
+	if (p->broken) {
 		*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		if (severity)
@@ -2788,7 +2786,7 @@ static int64_t phb3_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
 	int32_t i;
 	bool frozen_pe = false;
 
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/* Summary. If nothing, move to clearing the PESTs which can
@@ -2845,7 +2843,7 @@ static int64_t phb3_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
         struct phb3 *p = phb_to_phb3(phb);
         uint64_t data;
 
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	if (pe_number >= PHB3_MAX_PE_NUM)
@@ -2884,7 +2882,7 @@ static int64_t phb3_eeh_next_error(struct phb *phb,
 	int32_t i, j;
 
 	/* If the PHB is broken, we needn't go forward */
-	if (p->state == PHB3_STATE_BROKEN) {
+	if (p->broken) {
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		*severity = OPAL_EEH_SEV_PHB_DEAD;
 		return OPAL_SUCCESS;
@@ -3369,7 +3367,7 @@ static int64_t phb3_get_diag_data(struct phb *phb,
 
 	if (diag_buffer_len < sizeof(struct OpalIoPhb3ErrorData))
 		return OPAL_PARAMETER;
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/*
@@ -4373,7 +4371,7 @@ static void phb3_init_hw(struct phb3 *p, bool first_init)
 	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x2320d71600000000);
 
 	/* Mark the PHB as functional which enables all the various sequences */
-	p->state = PHB3_STATE_FUNCTIONAL;
+	p->broken = false;
 
 	PHBDBG(p, "Initialization complete\n");
 
@@ -4381,7 +4379,7 @@ static void phb3_init_hw(struct phb3 *p, bool first_init)
 
  failed:
 	PHBERR(p, "Initialization failed\n");
-	p->state = PHB3_STATE_BROKEN;
+	p->broken = true;
 }
 
 static void phb3_allocate_tables(struct phb3 *p)
@@ -4625,7 +4623,6 @@ static void phb3_create(struct dt_node *np)
 	p->phb.ops = &phb3_ops;
 	p->phb.phb_type = phb_type_pcie_v3;
 	p->phb.scan_map = 0x1; /* Only device 0 to scan */
-	p->state = PHB3_STATE_UNINITIALIZED;
 
 	if (!phb3_calculate_windows(p))
 		return;
diff --git a/hw/phb4.c b/hw/phb4.c
index 47175df2..e45be01f 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -274,7 +274,7 @@ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn,
 		return OPAL_HARDWARE;
 
 	/* Check PHB state */
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/* Fetch the PE# from cache */
@@ -2187,7 +2187,7 @@ static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
 	uint64_t hps, dtctl;
 
 	/* Test for PHB in error state ? */
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/* Check hotplug status */
@@ -2399,7 +2399,6 @@ static bool phb4_fenced(struct phb4 *p)
 
 	/* Mark ourselves fenced */
 	p->flags |= PHB4_AIB_FENCED;
-	p->state = PHB4_STATE_FENCED;
 
 	/* dump capp error registers in case phb was fenced due to capp */
 	if (nfir_n & XPEC_NEST_STK_PCI_NFIR_CXA_PE_CAPP)
@@ -2884,7 +2883,7 @@ static int64_t phb4_creset(struct pci_slot *slot)
 	uint64_t pbcq_status, reg;
 
 	/* Don't even try fixing a broken PHB */
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	switch (slot->state) {
@@ -2983,7 +2982,7 @@ static int64_t phb4_creset(struct pci_slot *slot)
 
 error:
 	/* Mark the PHB as dead and expect it to be removed */
-	p->state = PHB4_STATE_BROKEN;
+	p->broken = true;
 	return OPAL_HARDWARE;
 }
 
@@ -3087,7 +3086,7 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 	*pci_error_type = OPAL_EEH_NO_ERROR;
 
 	/* Check dead */
-	if (p->state == PHB4_STATE_BROKEN) {
+	if (p->broken) {
 		*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		if (severity)
@@ -3150,7 +3149,7 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
 	int32_t i;
 	bool frozen_pe = false;
 
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/* Summary. If nothing, move to clearing the PESTs which can
@@ -3207,7 +3206,7 @@ static int64_t phb4_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
 	struct phb4 *p = phb_to_phb4(phb);
 	uint64_t data;
 
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	if (pe_number >= p->num_pes)
@@ -3246,7 +3245,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
 	int32_t i, j;
 
 	/* If the PHB is broken, we needn't go forward */
-	if (p->state == PHB4_STATE_BROKEN) {
+	if (p->broken) {
 		*pci_error_type = OPAL_EEH_PHB_ERROR;
 		*severity = OPAL_EEH_SEV_PHB_DEAD;
 		return OPAL_SUCCESS;
@@ -3548,7 +3547,7 @@ static int64_t phb4_get_diag_data(struct phb *phb,
 
 	if (diag_buffer_len < sizeof(struct OpalIoPhb4ErrorData))
 		return OPAL_PARAMETER;
-	if (p->state == PHB4_STATE_BROKEN)
+	if (p->broken)
 		return OPAL_HARDWARE;
 
 	/*
@@ -4689,7 +4688,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
 	out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL,		0x2013000000000000ull);
 
 	/* Mark the PHB as functional which enables all the various sequences */
-	p->state = PHB4_STATE_FUNCTIONAL;
+	p->broken = false;
 
 	PHBDBG(p, "Initialization complete\n");
 
@@ -4697,7 +4696,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
 
  failed:
 	PHBERR(p, "Initialization failed\n");
-	p->state = PHB4_STATE_BROKEN;
+	p->broken = true;
 }
 
 /* FIXME: Use scoms rather than MMIO incase we are fenced */
@@ -4954,7 +4953,7 @@ static void phb4_err_interrupt(struct irq_source *is, uint32_t isn)
 				OPAL_EVENT_PCI_ERROR);
 
 	/* If the PHB is broken, go away */
-	if (p->state == PHB3_STATE_BROKEN)
+	if (p->broken)
 		return;
 
 	/*
@@ -5056,7 +5055,6 @@ static void phb4_create(struct dt_node *np)
 	p->phb.ops = &phb4_ops;
 	p->phb.phb_type = phb_type_pcie_v4;
 	p->phb.scan_map = 0x1; /* Only device 0 to scan */
-	p->state = PHB4_STATE_UNINITIALIZED;
 
 	if (!phb4_calculate_windows(p))
 		return;
@@ -5229,7 +5227,7 @@ static void phb4_create(struct dt_node *np)
 	return;
 
  failed:
-	p->state = PHB4_STATE_BROKEN;
+	p->broken = true;
 
 	/* Tell Linux it's broken */
 	dt_add_property_string(np, "status", "error");
diff --git a/include/p7ioc.h b/include/p7ioc.h
index 8040b3a9..96f9209c 100644
--- a/include/p7ioc.h
+++ b/include/p7ioc.h
@@ -146,68 +146,6 @@
 #define PHB_LSI_PCIE_UNUSED		6
 #define PHB_LSI_PCIE_ERROR		7
 
-/*
- * State structure for a PHB on P7IOC
- */
-
-/*
- * The PHB State structure is essentially used during PHB reset
- * or recovery operations to indicate that the PHB cannot currently
- * be used for normal operations.
- *
- * Some states involve waiting for the timebase to reach a certain
- * value. In which case the field "delay_tgt_tb" is set and the
- * state machine will be run from the "state_poll" callback.
- *
- * At IPL time, we call this repeatedly during the various sequences
- * however under OS control, this will require a change in API.
- *
- * Fortunately, the OPAL API for slot power & reset are not currently
- * used by Linux, so changing them isn't going to be an issue. The idea
- * here is that some of these APIs will return a positive integer when
- * needing such a delay to proceed. The OS will then be required to
- * call a new function opal_poll_phb() after that delay. That function
- * will potentially return a new delay, or OPAL_SUCCESS when the original
- * operation has completed successfully. If the operation has completed
- * with an error, then opal_poll_phb() will return that error.
- *
- * Note: Should we consider also returning optionally some indication
- * of what operation is in progress for OS debug/diag purposes ?
- *
- * Any attempt at starting a new "asynchronous" operation while one is
- * already in progress will result in an error.
- *
- * Internally, this is represented by the state being P7IOC_PHB_STATE_FUNCTIONAL
- * when no operation is in progress, which it reaches at the end of the
- * boot time initializations. Any attempt at performing a slot operation
- * on a PHB in that state will change the state to the corresponding
- * operation state machine. Any attempt while not in that state will
- * return an error.
- *
- * Some operations allow for a certain amount of retries, this is
- * provided for by the "retries" structure member for use by the state
- * machine as it sees fit.
- */
-enum p7ioc_phb_state {
-	/* First init state */
-	P7IOC_PHB_STATE_UNINITIALIZED,
-
-	/* During PHB HW inits */
-	P7IOC_PHB_STATE_INITIALIZING,
-
-	/* Set if the PHB is for some reason unusable */
-	P7IOC_PHB_STATE_BROKEN,
-
-	/* Set if the PHB is fenced due to an error */
-	P7IOC_PHB_STATE_FENCED,
-
-	/* PHB turned off by FSP (no clocks) */
-	P7IOC_PHB_STATE_OFF,
-
-	/* Normal PHB functional state */
-	P7IOC_PHB_STATE_FUNCTIONAL,
-};
-
 /* P7IOC PHB slot states */
 #define P7IOC_SLOT_NORMAL		PCI_SLOT_STATE_NORMAL
 #define P7IOC_SLOT_LINK			PCI_SLOT_STATE_LINK
@@ -290,7 +228,7 @@ struct p7ioc_phb {
 	uint8_t				index;	/* 0..5 index inside p7ioc */
 	uint8_t				gen;
 	uint32_t			flags;
-	enum p7ioc_phb_state		state;
+	bool				broken;
 #define P7IOC_REV_DD10	0x00a20001
 #define P7IOC_REV_DD11	0x00a20002
 	uint32_t			rev;	/* Both major and minor have 2 bytes */
diff --git a/include/phb3.h b/include/phb3.h
index 3f949fcc..bc46da7c 100644
--- a/include/phb3.h
+++ b/include/phb3.h
@@ -146,67 +146,6 @@
 #define PHB3_RESERVED_PE_NUM	255
 
 /*
- * State structure for a PHB
- */
-
-/*
- * (Comment copied from p7ioc.h, please update both when relevant)
- *
- * The PHB State structure is essentially used during PHB reset
- * or recovery operations to indicate that the PHB cannot currently
- * be used for normal operations.
- *
- * Some states involve waiting for the timebase to reach a certain
- * value. In which case the field "delay_tgt_tb" is set and the
- * state machine will be run from the "state_poll" callback.
- *
- * At IPL time, we call this repeatedly during the various sequences
- * however under OS control, this will require a change in API.
- *
- * Fortunately, the OPAL API for slot power & reset are not currently
- * used by Linux, so changing them isn't going to be an issue. The idea
- * here is that some of these APIs will return a positive integer when
- * neededing such a delay to proceed. The OS will then be required to
- * call a new function opal_poll_phb() after that delay. That function
- * will potentially return a new delay, or OPAL_SUCCESS when the original
- * operation has completed successfully. If the operation has completed
- * with an error, then opal_poll_phb() will return that error.
- *
- * Note: Should we consider also returning optionally some indication
- * of what operation is in progress for OS debug/diag purposes ?
- *
- * Any attempt at starting a new "asynchronous" operation while one is
- * already in progress will result in an error.
- *
- * Internally, this is represented by the state being P7IOC_PHB_STATE_FUNCTIONAL
- * when no operation is in progress, which it reaches at the end of the
- * boot time initializations. Any attempt at performing a slot operation
- * on a PHB in that state will change the state to the corresponding
- * operation state machine. Any attempt while not in that state will
- * return an error.
- *
- * Some operations allow for a certain amount of retries, this is
- * provided for by the "retries" structure member for use by the state
- * machine as it sees fit.
- */
-enum phb3_state {
-	/* First init state */
-	PHB3_STATE_UNINITIALIZED,
-
-	/* During PHB HW inits */
-	PHB3_STATE_INITIALIZING,
-
-	/* Set if the PHB is for some reason unusable */
-	PHB3_STATE_BROKEN,
-
-	/* PHB fenced */
-	PHB3_STATE_FENCED,
-
-	/* Normal PHB functional state */
-	PHB3_STATE_FUNCTIONAL,
-};
-
-/*
  * PHB3 PCI slot state. When you're going to apply any
  * changes here, please make sure the base state isn't
  * conflicting with those defined in pci-slot.h
@@ -267,7 +206,7 @@ struct phb3 {
 	unsigned int		index;	    /* 0..2 index inside P8 */
 	unsigned int		flags;
 	unsigned int		chip_id;    /* Chip ID (== GCID on P8) */
-	enum phb3_state		state;
+	bool			broken;
 	unsigned int		rev;        /* 00MMmmmm */
 #define PHB3_REV_MURANO_DD10	0xa30001
 #define PHB3_REV_VENICE_DD10	0xa30002
diff --git a/include/phb4.h b/include/phb4.h
index 757a3feb..4ab2912b 100644
--- a/include/phb4.h
+++ b/include/phb4.h
@@ -106,66 +106,6 @@
 #define PELTV_TABLE_SIZE_MAX	0x20000
 
 #define PHB4_RESERVED_PE_NUM(p)	((p)->num_pes - 1)
-/*
- * State structure for a PHB
- */
-
-/*
- * (Comment copied from p7ioc.h, please update both when relevant)
- *
- * The PHB State structure is essentially used during PHB reset
- * or recovery operations to indicate that the PHB cannot currently
- * be used for normal operations.
- *
- * Some states involve waiting for the timebase to reach a certain
- * value. In which case the field "delay_tgt_tb" is set and the
- * state machine will be run from the "state_poll" callback.
- *
- * At IPL time, we call this repeatedly during the various sequences
- * however under OS control, this will require a change in API.
- *
- * Fortunately, the OPAL API for slot power & reset are not currently
- * used by Linux, so changing them isn't going to be an issue. The idea
- * here is that some of these APIs will return a positive integer when
- * neededing such a delay to proceed. The OS will then be required to
- * call a new function opal_poll_phb() after that delay. That function
- * will potentially return a new delay, or OPAL_SUCCESS when the original
- * operation has completed successfully. If the operation has completed
- * with an error, then opal_poll_phb() will return that error.
- *
- * Note: Should we consider also returning optionally some indication
- * of what operation is in progress for OS debug/diag purposes ?
- *
- * Any attempt at starting a new "asynchronous" operation while one is
- * already in progress will result in an error.
- *
- * Internally, this is represented by the state being P7IOC_PHB_STATE_FUNCTIONAL
- * when no operation is in progress, which it reaches at the end of the
- * boot time initializations. Any attempt at performing a slot operation
- * on a PHB in that state will change the state to the corresponding
- * operation state machine. Any attempt while not in that state will
- * return an error.
- *
- * Some operations allow for a certain amount of retries, this is
- * provided for by the "retries" structure member for use by the state
- * machine as it sees fit.
- */
-enum phb4_state {
-	/* First init state */
-	PHB4_STATE_UNINITIALIZED,
-
-	/* During PHB HW inits */
-	PHB4_STATE_INITIALIZING,
-
-	/* Set if the PHB is for some reason unusable */
-	PHB4_STATE_BROKEN,
-
-	/* PHB fenced */
-	PHB4_STATE_FENCED,
-
-	/* Normal PHB functional state */
-	PHB4_STATE_FUNCTIONAL,
-};
 
 /*
  * PHB4 PCI slot state. When you're going to apply any
@@ -229,7 +169,7 @@ struct phb4 {
 	unsigned int		index;	    /* 0..5 index inside p9 */
 	unsigned int		flags;
 	unsigned int		chip_id;    /* Chip ID (== GCID on p9) */
-	enum phb4_state		state;
+	bool			broken;
 	unsigned int		rev;        /* 00MMmmmm */
 #define PHB4_REV_NIMBUS_DD10	0xa40001
 #define PHB4_REV_NIMBUS_DD20	0xa40002