diff options
| author | Alistair Popple <alistair@popple.id.au> | 2018-04-19 15:48:37 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-04-19 23:51:02 -0500 |
| commit | 0a4d0519a5a23ac11e06c3fc67fb04035716374f (patch) | |
| tree | 45eeaa7dc6005000bbc71857cf5f4c94eefdc484 | |
| parent | e148cb32cc2669b82f3cf4922ce3bf8caad88b60 (diff) | |
| download | talos-skiboot-0a4d0519a5a23ac11e06c3fc67fb04035716374f.tar.gz talos-skiboot-0a4d0519a5a23ac11e06c3fc67fb04035716374f.zip | |
hw/npu2.c: Remove static configuration of NPU2 register
The NPU_SM_CONFIG0 register currently needs to be configured in Skiboot to
select NVLink mode, however Hostboot should configure other bits in this
register.
For some reason Skiboot was explicitly clearing bit-6
(CONFIG_DISABLE_VG_NOT_SYS). It is unclear why this bit was getting cleared
as recent Hostboot versions explicitly set it to the correct value based on
the specific system configuration. Therefore Skiboot should not alter it.
Bit-58 (CONFIG_NVLINK_MODE) selects if NVLink mode should be enabled or
not. Hostboot does not configure this bit so Skiboot should continue to
configure it.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
| -rw-r--r-- | hw/npu2.c | 24 |
1 files changed, 12 insertions, 12 deletions
@@ -1368,18 +1368,18 @@ static void npu2_probe_phb(struct dt_node *dn) * * Obviously if the year is now 2020 that didn't happen and you * should fix this :-) */ - xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(58)); xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53)); xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53)); |
