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* p9c_mss_memdiags and p9c_mss_maint_cmdsLuke Mulkey2018-03-151-2/+2
| | | | | | | | | | | | | Change-Id: I5df92d15c23bbe0cf1eda7dfb68dfe70f54005f7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38948 Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55834 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add RCD_PARITY_ERROR enum value to ATTR_RECONFIGURE_LOOPcrgeddes2018-03-151-1/+2
| | | | | | | | | | | | | | | | | | | This attribute was missing the enum value on the EKB side. This caused problems when we attempted to generate all hb side of xml Change-Id: I463c6318fd796a1af5ec50a17323e7b68fe198e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41786 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55833 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Added RCD Protect time and MNFG Flag check to unmask functionMatthew Hickman2018-03-151-1/+1
| | | | | | | | | | | | | Change-Id: I641790e4300447caf78d54ab2b546cc90d796384 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37597 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55832 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add initial p9c ddr_phy_reset, dimmBadDqBitmapAccessHwp, slew, & unmask_errorsAndre Marin2018-03-151-1/+0
| | | | | | | | | | | | | | Change-Id: I1cbe3225208e6ee6c107ff84a9ebbb6248f0c7b8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35429 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35461 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Removing trailing comma in system_attributes.xmlBen Gass2018-03-151-1/+1
| | | | | | | | | | | | Change-Id: I1aa166a03bc139305983f037a4a00b18e34b0631 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37200 Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JOSHUA L. HANNAN <jlhannan@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55831 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Existing code changes for ddr_phy_reset HB mirrorLuke Mulkey2018-03-151-0/+48
| | | | | | | | | | | | | | | | | | | Change-Id: Ia4c701d93f0736b10ab7b5c2aa7859c2668f8706 Original-Change-Id: I45015e2967f719d2fd53be9faaf5cef0cd8457f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35842 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55830 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix bug in cache query state procedurePrasad Bg Ranganath2018-03-151-52/+66
| | | | | | | | | | | | | | | | Change-Id: I1f0fe8568bb0f4bfa003e35ef0873daf3b31c2f2 Original-Change-Id: Ic4869b2d73e90bd213c229fc83b189cb10ad57b6 CQ:SW407497 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49476 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55825 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Improve power and clock checking when checking for stop statesBrian Vanderpool2018-03-151-3/+7
| | | | | | | | | | | | | | | Change-Id: I3e5eeb48d182563a41046bc4c2dd378f08c99df2 Original-Change-Id: I62a9d62b61f9336d99459bca4090fb628f38787f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42499 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55824 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Honor STOP Gated bit when checking access statesDean Sanner2018-03-151-42/+47
| | | | | | | | | | | | | Change-Id: I08d2b377414f0f0491a731efee02359f6cefc27b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40920 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55823 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Change p9_mss_freq_system to write attributes, errors for CronusBrian Silver2018-03-151-11/+0
| | | | | | | | | | | | | | | | | | | | | | Honor the maximum support frequencies based on rank configs Remove the MEMVPD_FREQ attribute Fixup VPD tooling and accessors for new freq attrs Fix test case handling of master ranks Fix handling of empty MCS in Cronus Change-Id: I8344ca0bd3e6b8df11a9681dddf9d947d6cc096c Original-Change-Id: I669ad0e81454f12368b484e826461ee76f7b9079 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29878 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55829 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Changes related to packaging of memory vpd on Nimbuswhs2018-03-151-0/+11
| | | | | | | | | | | | | | | | | | | | Create a HWP to process MR and MT keyword to map to memory vpd keyword. Change specialization from MCS to MCA. Change-Id: I910be7012fb49494f2315ad05c6a8103baedfd8b Original-Change-Id: I426e4c7600e2158737c82e3c2380518c392ada5b RTC: 144519 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23775 Tested-by: Jenkins Server Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55828 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add base FAPI2 attribute definitionsJoe McGill2018-03-151-0/+49
| | | | | | | | | | | | | | | | | | Add attributes needed for Cronus platform compilation to hwpf/fapi2 Adjust location of XML in hwpf/fapi2 tree Change-Id: I82db640cdc678038820bf22c877b51e36aab3842 Original-Change-Id: I7c6873335bc21327edf53319bd0753c352205480 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20918 Tested-by: Jenkins Server Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Skip EQ_CLOCK_STAT_SL scom is we are in stop 11 or greatercrgeddes2018-03-151-19/+21
| | | | | | | | | | | | | | | | we shoulndt attempt to scom the EQ if the power is off Change-Id: I662a2bada8ed2991e7861aa5f4882f327630624c CQ: SW388687 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40563 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55822 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9_query_cache_access_state to use the correct scom registercrgeddes2018-03-141-2/+2
| | | | | | | | | | | | | | | | Found a bug in this HWP. It was using the Core scom address to scom the EQ target. The PPE putScom code must be smart enough to translate but the hostboot code was not so I had to fix this Change-Id: I4ea3991d8b36219b127299c38413bce0df7d101f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36829 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55821 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_query_cache_access_state L2CHRISTINA L. GRAVES2018-03-141-0/+173
| | | | | | | | | | | | Change-Id: Ibf4483f4875340b755f172201e7ff4e8f8ae5557 Original-Change-Id: I929f613a0574a982f414a79ca8cbc1580d36118e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30918 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55820 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add p9n 2.3 to p9_frequency_buckets.HBen Gass2018-03-131-0/+7
| | | | | | | | | | | | | | | | Change-Id: I06f679f555c5dfd0a66f5b9bc5ff1e3424c4aae7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55383 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Dev-Ready: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55390 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Change TP FIR bits 38, 39, 40 as recoverable & MaskedSoma BhanuTej2018-03-131-2/+2
| | | | | | | | | | | | | | Change-Id: Ib21a9940b9b458a74d24a4a6bf1ad734ec4896c3 CQ: SW419535 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54951 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54955
* PM: p9_setup_evid steps voltage to avoid Fleetwood VRM limitationsGreg Still2018-03-131-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | - use the present value of ATTR_EXT_VRM_STEPSIZE (used by PGPE for Pstate movement) to step the the boot voltage setup during istep 8. This attribute defaults to 50mV. - Done only for rails attached via AVSBus Key_Cronus_Test=PM_REGRESS Change-Id: I63feb361323246c8b92f1e96dc41f8fc19bd0912 CQ: SW420343 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55386 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55393 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9_collect_ppe_state to dynamically collect PPE FFDCAmit Tendolkar2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | 1- On FSP, avoid RAMming and collect only XIRs 2- On Host: avoid side effects of having to Halt PPE for RAMming: a Avoid Halt, if not already halted or in PMReset, collect only XIRs b Collect max state if already halted, no side-effects Change-Id: I7b27a02aebda0122f7dd7e36eaff869a510e5af5 CQ: SW419011 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54368 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55010 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding attribute to detect which processor we can use for alt-memoryElizabeth Liner2018-03-072-0/+16
| | | | | | | | | | | | | | | | Change-Id: I5e0435c5828dcaddb8571afdbd298c08400cb0e4 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54585 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54598
* p9_sbe_tracearray -- satsify PRD calls to manage core trace arraysJoe McGill2018-03-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a carryover from prior projects, PRD code currently contains logic which attempts to restart the core trace arrays (via the SBE HWP) after processing a recoverable error emitted from the core. The current HWP flags an error in this case (indicating that the core trace arrays are not SCOM retrievable, which is true for all levels of p9). This generates a customer visible error log with a FW type callout, which is undesirable. This patch is intended to satisfy the current PRD call which intends to reset and start the core traces, without triggering the check mentioned above or attempting to access non-implemented SCOM registers. Ultimately it should have no effect on the actual core tracing, which is managed on p9 by non-SCOM accessible logic in PC. I confirmed with Jim Bishop that the PC logic will not stop tracing on recoverable errors, so there should be no exposure. Change-Id: I77e47f71d18b6a3a762ab52b0f6b42d022153f3b CQ: SW418341 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54857 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54861 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix a couple of EKB files to prevent CMVC quirkaravnair-in2018-03-062-3/+3
| | | | | | | | | | | | | | | | | | | | CMVC expands the date command strings added as comments in these two files. So when we try using the auto code checkin tool to push code from hwsv Git repo to CMVC, we end up checking in these files always - as they show the current date versus the actual date command strings. Change-Id: Ibe82b679f14d781c7b64ae8dcdd7ab2356accf8d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54830 Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54836
* Disable WOF for Cumulus DD1.0Dan Crowell2018-03-051-0/+7
| | | | | | | | | | | | | | Change-Id: I4d4704098f92004f5a6a141e16b80a2b2dd2a3ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54925 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54932 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable risklevel2, match v44 of security wikiNick Klazynski2018-03-021-3/+3
| | | | | | | | | | | | | | | Change-Id: I9ee4a8c97705ea5aa984c2c0137ed012d50eb658 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54711 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54720 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone support to TP stopclocksSoma BhanuTej2018-03-025-46/+125
| | | | | | | | | | | | | | | | | | Change-Id: I0960ec588156f3df3f863b6c5fa41bbed95e089e RTC: 183048 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53139 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53152 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone MC uses same pll/clock setup as in Cumulus.Ben Gass2018-03-011-1/+16
| | | | | | | | | | | | | | | | | Set HW426891 attribute for Axone. Change-Id: I2c023f3f7cd4060d5acd9bc7ce39bd58b5c56c05 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54069 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54076 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update to putRingUtils to proper scanning of perv_pll_bndy_flt ringsClaus Michael Olsen2018-02-282-6/+15
| | | | | | | | | | | | | | | | | | I've updated p9_putRingUtils.C for SBE to make sure we do a 1-bit boundary scanning for the perv_pll_bndy_flt rings since they are override rings by nature. Change-Id: I1c8a63708c571f67be5359b1a0e4a9b050a8275b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54575 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54587 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: Support Suspend Entry/Exit and Fix Pig CollisionYue Du2018-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | 1) also cleanup todos in Stop Hcode 2) make STOP3 complete trans in SSH Key_Cronus_Test=PM_REGRESS Change-Id: I28a146e15e455f09f8d8ff588e122d5ecf34110a CQ: SW416550 CQ: HW437955 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54660 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54664 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add support for p9c 1.2Ben Gass2018-02-236-20/+80
| | | | | | | | | | | | | | | | | Also initial mk files for p9n 2.3, but p9c 1.2 will be first. Change-Id: Ia73aba37be5bcf64b1b2cfe5b1ed153b189c7777 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53909 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54542 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add Cumulus DD1.1 initsNick Klazynski2018-02-231-46/+291
| | | | | | | | | | | | | | | | | | | | | | | CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 cmvc-prereq: 1046552 cmvc-prereq: 1045908 Change-Id: I3752f5b5868d7cc8ed3ffdf69a13025989a47eaa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54270 Dev-Ready: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54284 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add EQ ATOMIC LOCK SCOM to security write whitelist for FFDCAmit Tendolkar2018-02-231-0/+1
| | | | | | | | | | | | | | | | | | Special wakeup fails from FSP need to colect some CME SCOMs that can be accessed after grabbing this lock. Does not comprise access to any sensitive hardware / firmware facility Change-Id: If074c73478f2d8feb586c41aee8eb49b8a9fce6a CQ: SW417220 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54429 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54436 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM_SPWKUP: Clear wakeup notify select bit to enable auto special wakeupGreg Still2018-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | - Deal with Hostboot cores coming out of istep 4 Key_Cronus_Test=PM_REGRESS Change-Id: Ie990d82eed0cb5ab3c71752a557d2f5b197d5642 CQ:SW412666 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54140 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54166 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* LPC: Add empty files for mirroring to HB, PPE, HWSVJoachim Fenkes2018-02-222-0/+50
| | | | | | | | | | Change-Id: If904019d1a847136be3e553302ab5e29ae0a8f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54482 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54508 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Additional risk level support - (step 2) Updating the image w/RL2Claus Michael Olsen2018-02-173-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322
* Updating NCU tlbie pacing dialsLuke C. Murray2018-02-171-4/+4
| | | | | | | | | | | | | | | | | | | This setting improves tlbie latencies that were measured on IBMi. Also commit generated initfile changes causing Jenkins compliation failure. Change-Id: I206fa3c8f07859d44f6f82f3eadebf6f11352637 CQ: HW438757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54157 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54179 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add attribute to give platform more control over PM_RESETChristian Geddes2018-02-161-1/+17
| | | | | | | | | | | | | | | | | | | | | | | The PM_RESET hwp calls special wakeup enable on all EX targets, then will clear auto-special wakeup bit on the core if special wakeup is done. In some cases hostboot does not want these steps of the PM_RESET. This attribute gives the platform the ability to decide if they want to enable special wakeup and clear autowakeup on the cores during PM_RESET CQ:SW412666 Change-Id: I8f2e40f4b122f3ff6a048fa6931a1e47f89d3e4f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53953 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53991 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* hwpErrors: Use wildcard instead of explicit listJoachim Fenkes2018-02-162-88/+2
| | | | | | | | | | | | The makefile was including all XMLs but one (that was unused) anyway. Switch to wildcard so we don't have to explicitly touch hwpErrors.mk every time we add an error XML file. Change-Id: I127dcb75ab3ecb0dadaf73e06d6f6fd3e8294524 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54212 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Protect Firmware from exposure to HW423533Lennard Streat2018-02-151-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iaf1a83505ed9bdd9e79bfc46157856263c392736 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53783 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53802 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add TM WAT workaround; NDD2.2 and CDD1.1 onlyNick Klazynski2018-02-151-0/+24
| | | | | | | | | | | | | | | | Change-Id: I376860a1530ce8ba467d18ea97c0da4e6672e53f CQ: HW436858 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54056 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54073 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disabling WOF and VDM for Nimbus DD2.0Dan Crowell2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Modified the checks to disable WOF by default for Nimbus DD2.0 since most parts have invalid module vpd. Also changed the severity that is used to log errors getting a WOF table to make them visible logs. Without this change we won't know why the lookup failed in many cases. Change-Id: Ic8fd9b4bdc23311897363552f0c88fa2b1b0247b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53274 Reviewed-by: Francesco A. Campisano <campisan@us.ibm.com> Dev-Ready: Francesco A. Campisano <campisan@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53288 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Re-submit Axone updatesBen Gass2018-02-155-38/+267
| | | | | | | | | | | | | | | | | | | | | | | The original patch: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/45266/ was merged prematurely. It was reverted in: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/50703/ pre-commit-actions updated to call code-beautifier twice. Some generated code for initfiles changes between first and second passes. Change-Id: I25bdc2ceaf9636a2f6559775bc8cb9616848c9d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50741 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50961 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FIR + RAS XML updatesJoe McGill2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | p9_sbe_scominit.C mask PBCENT FIR bit 5, rely on action of unit master specific FIR bits to drive attention generation on any cresp address error condition Change-Id: I3c23aeecd426687fe91d37aadfd5ca6243c4a4b3 CQ: SW417475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54067 Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Mask TP LFIR for non PPE mode - p9_sbe_commonSoma BhanuTej2018-02-151-1/+9
| | | | | | | | | | | | | Change-Id: Ib8940710cadc62228be70bf60e98673ece171e10 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54024 Reviewed-by: PRADEEP N. CHATNAHALLI <pradeepcn@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54025
* Extend PM Reset flow to collect PM FFDC to HOMERAmit Tendolkar2018-02-152-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | - extend the base flow to ensure ffdc gets collected to homer - revise error xmls - misc changes to handle pm recovery flow triggered via Malf Alert Key_Cronus_Test=PM_REGRESS Change-Id: I12148ed227efe4613332ae76ff142c1d82855f20 RTC: 153979 CQ: SW416537 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53522 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53532 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Bug fix to TOR API to not check TOR header version against TOR_VERSIONClaus Michael Olsen2018-02-141-1/+0
| | | | | | | | | | | | | | | | | | I'm removing this check because it is not a valid check for making a decision that the TOR header is invalid (it's still valid). CQ: SW416424 Change-Id: I2cdb78bc18a1fcc718038be41b2965255ba5d0de Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54017 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54022
* Enable mixed core xlate; Enable xlate protection feature; Disable LSU clockgateNick Klazynski2018-02-131-0/+72
| | | | | | | | | | | | | | | | | Change-Id: I1fbc2c79330520d6033adfafe85a89fc71ed3fb0 CQ: HW437820 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53911 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53917 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix to TOR API failure on 32b systemsClaus Michael Olsen2018-02-131-1/+6
| | | | | | | | | | | | | | | | | | | | | | This fixes a bug wrt incorrect use of sizeof() on a pointer that only shows up on 32b system (but is luckily successful on 64b systems). Key_Cronus_Test=XIP_REGRESS Change-Id: I9f33c5728cb68acaeee55580c9f1c1b8743cbd8d CQ: SW412437 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53875 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53904
* Secure Boot: Blacklist: Finalize SBE white/blacklistNick Bofferding2018-02-121-31/+7
| | | | | | | | | | | | | | | | Remove all existing TODOs/workarounds in SBE white/blacklist Change-Id: Iebfdb2f3b0e064a31a143746dbb6952e0458f869 CQ: SW408603 Backport: release-fips910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53688 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53693
* enforce strict 512 GB per socket limit on Witherspoon memory map (part2)Joe McGill2018-02-122-3/+6
| | | | | | | | | | | | | | | | | | | | | | | first commit merged before HW testing was complete, and caused issue with skiboot's detection of the MCD workaround mechanism this update restores the chip address extension HW programming to 0x7, (to avoid a coreq skiboot change) but should still restrict the allocation to lie within the first 512 GB of address space on each socket Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53642 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enforce strict 512 GB per socket limit on Witherspoon memory mapJoe McGill2018-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SW415901 exposed a problem with the current implementation of extended addressing for Witherspoon Coral systems. With fully configured memory present in the system (8x64GB=512GB per socket), GARDing a DIMM will currently result in: - group of 6 fullying occupying 0-512GB address space - group of 1 mapped at 8TB region (2nd extended addressing region) The single group mapping has RA bit 20 active, which is problematic for the NVIDIA device driver. p9_fbc_utils.H p9.trace.scan.initfile for HW423589 option 2, enable chip address extension for chip ID LSB RA bit 21 only. This creates only one 4TB extended addressing region per socket. indirectly, this limits DIMMs to map into the 512 GB region with RA bit 21=0 and should cause an IPL failure if more than 512 GB is plugged or the memory grouping algorithm attempts to spill beyond 512 GB on a given chip p9_mss_eff_grouping.C prohibit formation of group sizes 6 and 3 when HW423589 option2 WA is active Change-Id: I997c080a2821cf3c556a4f8b35d5e0fdb34da500 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53411 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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