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* Adding p9n 2.3 support and p9n 2.3/p9c 1.2 security updateBen Gass2018-04-205-44/+103
| | | | | | | | | | | | | | | | CMVC-Prereq: 1051830 Change-Id: I21b0d9187443f2727f83df310bca2fb3ae0fd80c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55376 Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56834 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert changes to EFF_FBC_GRP_CHIP_IDS modespashabk-in2018-04-202-7/+5
| | | | | | | | | | | | | | | | Change-Id: I4907eea62c2fa85bdf9ed193d1820fba84afc82f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57530 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57534 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Clean up PM Reset and PM Complex SuspendChristian Geddes2018-04-201-2/+2
| | | | | | | | | | | | | | | | | | | | - Increase timeout in PM Complex Suspend from 10ms -> 500ms - Disable CME monitoring of PGPE heart beat loss before halting PGPE Key_Cronus_Test=PM_REGRESS Change-Id: I3fbb435ce694e7590e9e9570107347a621828402 CQ: SW424102 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56884 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56903
* make ATTR_START_CBS_FIFO_RESET_SKIP platInitMatt K. Light2018-04-181-0/+1
| | | | | | | | | | | | | | | Change-Id: Ia995817f30cca235b8c725feec27f7a14f26f924 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43311 Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43317
* Adding changes to handle core checkstopsElizabeth Liner2018-04-182-2/+23
| | | | | | | | | | | | | | | | | | | | | At certain points during the IPL, we need to turn off unit checkstops and switch them to system checkstops. This HWP saves off the original value, turns unit to system checkstops, and then later restores them. Change-Id: Iebd1d4c5b69eae04f05b890c879d8dd88f0655d3 RTC:147565 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56331 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_hcd_cache_scominit -- disable LCO unless using force_all_coresJoe McGill2018-04-181-2/+2
| | | | | | | | | | | | | | Change-Id: I938d01f60907444b65b2f3b08d0fdfc59433dc79 CQ: SW424941 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57399 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57404 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fenced Enabled check along with vdd_pfet_disable_core for scomsRaja Das2018-04-171-6/+16
| | | | | | | | | | | | | | | | | In core stopstate2, only checking the vdd_pfet_disable_core is not enough before scoming for C_CLOCK_STAT_SL, since in stopstate2 fences are up, so need to check for fenced bit as well in C_NET_CTRL0 reg. Change-Id: If99dd3d357b6e07c56417edae0868c03f2f0b720 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52993 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53809
* Consume PROC_MEM_TO_USE for alt memory configspashabk-in2018-04-164-26/+25
| | | | | | | | | | | | | | | Change-Id: Ideb3c3d2bbdbce8b773d51b86d9f97f2e654ca56 RTC:189091 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56197 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56203
* Add PROC_MEM_TO_USE to SBEspashabk-in2018-04-131-1/+1
| | | | | | | | | | | | | Change-Id: I614bf9b59166dadd84ea5276845f2cd7d897c2cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57053 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57056
* Temporarily moving attribute to the system targetElizabeth Liner2018-04-101-0/+12
| | | | | | | | | | | | | | | | | | | | There were dependency issues between the FSP and hostboot changes. This commit is temporarily moving everything to the system target, so that we can get our changes through CI. We'll go back later and fix the target to the proc Change-Id: Ic2d63d10afe50342290a814a94fd2d07d7102fdf RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56814 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56825
* Abist proc update for SBE changesAbhishek Agarwal2018-04-092-0/+21
| | | | | | | | | | | | | | | Change-Id: I28a11ecc5f64498f495f1575c914c5d3120c6f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54243 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56789 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_lpc_init: Fix cycle sim delay loopSoma BhanuTej2018-04-051-2/+3
| | | | | | | | | | | | | | | | | | Adding additional delay during polling for LPC status Issue encountered in GSD2PIB mode Awan simulations only Change-Id: I220843de8c37fa578ea26ea253345a380666a1d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56724 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56779 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* move xlink psave configuration to SBEJoe McGill2018-04-031-1/+29
| | | | | | | | | | | | | | | | | | | | | | | 55058 added inits to prime the PPE for xlink psave the register touched is in the blacklist, so it can't be touched on slave chips via FSI in the ioe tl SCOM initifle -- this was triggering HW CI failures this commit simply shifts the register setup into the SBE, where it can be performed securely Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059 CQ: SW421691 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating ATTR_PROC_CHIP_MEM_TO_USE to use all bits of group and chip IDElizabeth Liner2018-04-021-1/+1
| | | | | | | | | | | | | | | | | | When first created, we assumed the group ID and chip ID's were both 2 bits, but they're actually 3. This is updating the attribute. Change-Id: Iabc112f7202d410bd7bceab53c3ad79a1df17368 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56039 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56498
* Pass SBE Security Backdoor Bit to HB BootloaderIlya Smirnov2018-04-024-6/+14
| | | | | | | | | | | | | | | | | | | | Add a "SBE security backdoor" bit to reflect the state of the SBE security backdoor; the bit is passed to the hostboot bootloader from SBE. The new bit is the inverse of the ATTR_SECURITY_MODE attribute. Also bump the version of SBE/bootloader to reflect the change. Change-Id: Idf3009447c51c66306c043daf7f8189b8cbf2f36 RTC:188961 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56309 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56318
* PGPE: Error Handling SupportRahul Batra2018-04-021-29/+38
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I00aca629108aeaca88db34eec8e408f3cd48ff7f CQ: SW414842 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48635 Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53326 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Turn off PB.IOO.LL0.CONFIG_FAST_ASYNC_CROSS for Nimbus (HW409026)Ben Gass2018-03-291-0/+18
| | | | | | | | | | | | | | | | | | | | | Due to HW409026, PB.IOO.LL0.CONFIG_FAST_ASYNC_CROSS should be off for all Nimbus chips. Change-Id: Ib732be7ce3d3e64e3c0b9112a088bb9a8fed14c4 CQ: SW420220 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: ADRIAN BARRERA <abarrera@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jeffrey W. Kellington <jwkellin@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54800 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Do not apply HW414958 to AxoneThi Tran2018-03-281-3/+28
| | | | | | | | | | | | | | | Change-Id: I6fcbc5f49fdce481c9525220bc69ad9c4e1ecf1b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55945 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56014 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW438727 Disable clockgate to allow correct ODL error reportingJenny Huynh2018-03-281-0/+25
| | | | | | | | | | | | | | | | | | | | Additional change to scan init obus fir mask to all 1's to avoid any false reporting early in the IPL. Change-Id: I1501a050af5f723d968e5bfbb965d1ae3b567a97 CQ:HW438727 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54417 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54424 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Scommable check before L2/L3 Purge in MPIPL PathRaja Das2018-03-221-0/+7
| | | | | | | | | | | CQ: SW420347 Change-Id: I051b8ff4a0afadb311db24f1c235fdc1a433958f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55838 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Mask off bit 26 of TP_LFIR on FSP machinesSoma BhanuTej2018-03-211-1/+8
| | | | | | | | | | | | | | Change-Id: Ided77a0645e4f657b326ba5ec63f7c35ab6b2029 CQ: SW421112 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55906 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55907
* p9_sbe_lpc_init: Fix timeout setupJoachim Fenkes2018-03-194-39/+139
| | | | | | | | | | | | | | | | | | | | Factor LPC register access out into its own utility function, with added timeout for the ADU access and proper FFDC if the ADU times out. CQ: SW418354 cmvc-prereq: 1048349 Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54641 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove CDD1.1 security IMC; Apply indirect branch serialization to HV=0 onlyNick Klazynski2018-03-191-17/+0
| | | | | | | | | | | | | | | Change-Id: I685b5608eb0fbfba755a50b0b0f27fc4d77a2d78 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55040 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55053 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: Fix Wakeup terminate prematurely with mixed stop2 and stop4Yue Du2018-03-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This bug only impact when one core engages the error path As one core detects xstop or fail to startclocks, while we intend to bypass the error core and move on with the good remaining core, whose wakeup will be lost due to the bug Key_Cronus_Test=PM_REGRESS Change-Id: I27012164095b99429d8c46dca5b1c8b3da62e135 CQ: SW420556 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54833 Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54849 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix bug in cache query state procedurePrasad Bg Ranganath2018-03-151-52/+66
| | | | | | | | | | | | | | | | Change-Id: I1f0fe8568bb0f4bfa003e35ef0873daf3b31c2f2 Original-Change-Id: Ic4869b2d73e90bd213c229fc83b189cb10ad57b6 CQ:SW407497 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49476 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55825 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Improve power and clock checking when checking for stop statesBrian Vanderpool2018-03-151-3/+7
| | | | | | | | | | | | | | | Change-Id: I3e5eeb48d182563a41046bc4c2dd378f08c99df2 Original-Change-Id: I62a9d62b61f9336d99459bca4090fb628f38787f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42499 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55824 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Honor STOP Gated bit when checking access statesDean Sanner2018-03-151-42/+47
| | | | | | | | | | | | | Change-Id: I08d2b377414f0f0491a731efee02359f6cefc27b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40920 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55823 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Skip EQ_CLOCK_STAT_SL scom is we are in stop 11 or greatercrgeddes2018-03-151-19/+21
| | | | | | | | | | | | | | | | we shoulndt attempt to scom the EQ if the power is off Change-Id: I662a2bada8ed2991e7861aa5f4882f327630624c CQ: SW388687 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40563 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55822 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9_query_cache_access_state to use the correct scom registercrgeddes2018-03-141-2/+2
| | | | | | | | | | | | | | | | Found a bug in this HWP. It was using the Core scom address to scom the EQ target. The PPE putScom code must be smart enough to translate but the hostboot code was not so I had to fix this Change-Id: I4ea3991d8b36219b127299c38413bce0df7d101f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36829 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55821 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_query_cache_access_state L2CHRISTINA L. GRAVES2018-03-141-0/+173
| | | | | | | | | | | | Change-Id: Ibf4483f4875340b755f172201e7ff4e8f8ae5557 Original-Change-Id: I929f613a0574a982f414a79ca8cbc1580d36118e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30918 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55820 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Change TP FIR bits 38, 39, 40 as recoverable & MaskedSoma BhanuTej2018-03-131-2/+2
| | | | | | | | | | | | | | Change-Id: Ib21a9940b9b458a74d24a4a6bf1ad734ec4896c3 CQ: SW419535 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54951 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54955
* PM: p9_setup_evid steps voltage to avoid Fleetwood VRM limitationsGreg Still2018-03-131-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | - use the present value of ATTR_EXT_VRM_STEPSIZE (used by PGPE for Pstate movement) to step the the boot voltage setup during istep 8. This attribute defaults to 50mV. - Done only for rails attached via AVSBus Key_Cronus_Test=PM_REGRESS Change-Id: I63feb361323246c8b92f1e96dc41f8fc19bd0912 CQ: SW420343 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55386 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55393 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9_collect_ppe_state to dynamically collect PPE FFDCAmit Tendolkar2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | 1- On FSP, avoid RAMming and collect only XIRs 2- On Host: avoid side effects of having to Halt PPE for RAMming: a Avoid Halt, if not already halted or in PMReset, collect only XIRs b Collect max state if already halted, no side-effects Change-Id: I7b27a02aebda0122f7dd7e36eaff869a510e5af5 CQ: SW419011 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54368 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55010 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding attribute to detect which processor we can use for alt-memoryElizabeth Liner2018-03-072-0/+16
| | | | | | | | | | | | | | | | Change-Id: I5e0435c5828dcaddb8571afdbd298c08400cb0e4 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54585 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54598
* p9_sbe_tracearray -- satsify PRD calls to manage core trace arraysJoe McGill2018-03-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a carryover from prior projects, PRD code currently contains logic which attempts to restart the core trace arrays (via the SBE HWP) after processing a recoverable error emitted from the core. The current HWP flags an error in this case (indicating that the core trace arrays are not SCOM retrievable, which is true for all levels of p9). This generates a customer visible error log with a FW type callout, which is undesirable. This patch is intended to satisfy the current PRD call which intends to reset and start the core traces, without triggering the check mentioned above or attempting to access non-implemented SCOM registers. Ultimately it should have no effect on the actual core tracing, which is managed on p9 by non-SCOM accessible logic in PC. I confirmed with Jim Bishop that the PC logic will not stop tracing on recoverable errors, so there should be no exposure. Change-Id: I77e47f71d18b6a3a762ab52b0f6b42d022153f3b CQ: SW418341 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54857 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54861 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable WOF for Cumulus DD1.0Dan Crowell2018-03-051-0/+7
| | | | | | | | | | | | | | Change-Id: I4d4704098f92004f5a6a141e16b80a2b2dd2a3ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54925 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54932 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable risklevel2, match v44 of security wikiNick Klazynski2018-03-021-3/+3
| | | | | | | | | | | | | | | Change-Id: I9ee4a8c97705ea5aa984c2c0137ed012d50eb658 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54711 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54720 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone support to TP stopclocksSoma BhanuTej2018-03-025-46/+125
| | | | | | | | | | | | | | | | | | Change-Id: I0960ec588156f3df3f863b6c5fa41bbed95e089e RTC: 183048 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53139 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53152 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone MC uses same pll/clock setup as in Cumulus.Ben Gass2018-03-011-1/+16
| | | | | | | | | | | | | | | | | Set HW426891 attribute for Axone. Change-Id: I2c023f3f7cd4060d5acd9bc7ce39bd58b5c56c05 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54069 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54076 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: Support Suspend Entry/Exit and Fix Pig CollisionYue Du2018-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | 1) also cleanup todos in Stop Hcode 2) make STOP3 complete trans in SSH Key_Cronus_Test=PM_REGRESS Change-Id: I28a146e15e455f09f8d8ff588e122d5ecf34110a CQ: SW416550 CQ: HW437955 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54660 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54664 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add support for p9c 1.2Ben Gass2018-02-235-20/+73
| | | | | | | | | | | | | | | | | Also initial mk files for p9n 2.3, but p9c 1.2 will be first. Change-Id: Ia73aba37be5bcf64b1b2cfe5b1ed153b189c7777 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53909 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54542 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add Cumulus DD1.1 initsNick Klazynski2018-02-231-46/+291
| | | | | | | | | | | | | | | | | | | | | | | CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 cmvc-prereq: 1046552 cmvc-prereq: 1045908 Change-Id: I3752f5b5868d7cc8ed3ffdf69a13025989a47eaa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54270 Dev-Ready: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54284 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM_SPWKUP: Clear wakeup notify select bit to enable auto special wakeupGreg Still2018-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | - Deal with Hostboot cores coming out of istep 4 Key_Cronus_Test=PM_REGRESS Change-Id: Ie990d82eed0cb5ab3c71752a557d2f5b197d5642 CQ:SW412666 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54140 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54166 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* LPC: Add empty files for mirroring to HB, PPE, HWSVJoachim Fenkes2018-02-222-0/+50
| | | | | | | | | | Change-Id: If904019d1a847136be3e553302ab5e29ae0a8f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54482 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54508 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Additional risk level support - (step 2) Updating the image w/RL2Claus Michael Olsen2018-02-172-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322
* Updating NCU tlbie pacing dialsLuke C. Murray2018-02-171-4/+4
| | | | | | | | | | | | | | | | | | | This setting improves tlbie latencies that were measured on IBMi. Also commit generated initfile changes causing Jenkins compliation failure. Change-Id: I206fa3c8f07859d44f6f82f3eadebf6f11352637 CQ: HW438757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54157 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54179 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add attribute to give platform more control over PM_RESETChristian Geddes2018-02-161-1/+17
| | | | | | | | | | | | | | | | | | | | | | | The PM_RESET hwp calls special wakeup enable on all EX targets, then will clear auto-special wakeup bit on the core if special wakeup is done. In some cases hostboot does not want these steps of the PM_RESET. This attribute gives the platform the ability to decide if they want to enable special wakeup and clear autowakeup on the cores during PM_RESET CQ:SW412666 Change-Id: I8f2e40f4b122f3ff6a048fa6931a1e47f89d3e4f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53953 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53991 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* hwpErrors: Use wildcard instead of explicit listJoachim Fenkes2018-02-162-88/+2
| | | | | | | | | | | | The makefile was including all XMLs but one (that was unused) anyway. Switch to wildcard so we don't have to explicitly touch hwpErrors.mk every time we add an error XML file. Change-Id: I127dcb75ab3ecb0dadaf73e06d6f6fd3e8294524 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54212 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Protect Firmware from exposure to HW423533Lennard Streat2018-02-151-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iaf1a83505ed9bdd9e79bfc46157856263c392736 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53783 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53802 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add TM WAT workaround; NDD2.2 and CDD1.1 onlyNick Klazynski2018-02-151-0/+24
| | | | | | | | | | | | | | | | Change-Id: I376860a1530ce8ba467d18ea97c0da4e6672e53f CQ: HW436858 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54056 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54073 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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