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| author | spashabk-in <shakeebbk@in.ibm.com> | 2018-03-23 06:09:42 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-04-16 12:39:23 -0400 |
| commit | be846edf5a2fae95ffdb81b626410d35d435fcd7 (patch) | |
| tree | 47b81cdb995faa747e9a9c080ad4aa0d1f8e2986 /src/import/chips/p9/procedures | |
| parent | aa83a786a35d5fc48f90c1a5de13d6e818a77404 (diff) | |
| download | talos-sbe-be846edf5a2fae95ffdb81b626410d35d435fcd7.tar.gz talos-sbe-be846edf5a2fae95ffdb81b626410d35d435fcd7.zip | |
Consume PROC_MEM_TO_USE for alt memory config
Change-Id: Ideb3c3d2bbdbce8b773d51b86d9f97f2e654ca56
RTC:189091
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56197
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56203
Diffstat (limited to 'src/import/chips/p9/procedures')
4 files changed, 25 insertions, 26 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index feea764d..ee602beb 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -67,6 +67,12 @@ const uint8_t FABRIC_ADDR_LS_GROUP_ID_END_BIT = 18; // chip ID (large system) const uint8_t FABRIC_ADDR_LS_CHIP_ID_START_BIT = 19; const uint8_t FABRIC_ADDR_LS_CHIP_ID_END_BIT = 21; +// memory group/chip ID +const uint8_t FABRIC_ADDR_MEMORY_GROUP_ID_START_BIT = 0; +const uint8_t FABRIC_ADDR_MEMORY_GROUP_ID_LEN = 3; +const uint8_t FABRIC_ADDR_MEMORY_CHIP_ID_START_BIT = 3; +const uint8_t FABRIC_ADDR_MEMORY_CHIP_ID_LEN = 3; + //------------------------------------------------------------------------------ @@ -158,6 +164,7 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( uint8_t l_fabric_chip_id = 0; uint8_t l_mirror_policy; fapi2::buffer<uint64_t> l_base_address; + fapi2::buffer<uint8_t> l_proc_chip_mem_to_use = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; FAPI_DBG("Start"); @@ -167,34 +174,28 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fabric_system_id), "Error from FAPI_ATTR_GET (ATTR_FABRIC_SYSTEM_ID)"); - // set group ID - if ((i_addr_mode == ABS_FBC_GRP_CHIP_IDS) || - (i_addr_mode == ABS_FBC_GRP_ID_ONLY)) + if (i_addr_mode == HB_GRP_CHIP_IDS) { - // absolute - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id), + // HB group/chip ID + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_MEM_TO_USE, + i_target, + l_proc_chip_mem_to_use), "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)"); - } - else - { - // effective - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target, l_fabric_group_id), - "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_GROUP_ID)"); - } - // set chip ID - if (i_addr_mode == ABS_FBC_GRP_CHIP_IDS) - { - // absolute - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id), - "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)"); + l_proc_chip_mem_to_use.extract<FABRIC_ADDR_MEMORY_GROUP_ID_START_BIT, + FABRIC_ADDR_MEMORY_GROUP_ID_LEN, + 0>(l_fabric_group_id); + l_proc_chip_mem_to_use.extract<FABRIC_ADDR_MEMORY_CHIP_ID_START_BIT, + FABRIC_ADDR_MEMORY_CHIP_ID_LEN, + 0>(l_fabric_chip_id); } else if (i_addr_mode == EFF_FBC_GRP_CHIP_IDS) { // effective + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target, l_fabric_group_id), + "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_GROUP_ID)"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fabric_chip_id), "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_CHIP_ID)"); - } // else, leave chip ID=0 for the purposes of establishing drawer base address diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 6a0c0a35..d1f64d1f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -52,9 +52,7 @@ enum p9_fbc_utils_addr_mode_t { EFF_FBC_GRP_CHIP_IDS, // effective FBC group/chip ID attributes - EFF_FBC_GRP_ID_ONLY, // effective FBC group ID attribute (chip ID=0) - ABS_FBC_GRP_CHIP_IDS, // absolute FBC group/chip ID attributes - ABS_FBC_GRP_ID_ONLY // absolute FBC group ID attribute (chip ID=0) + HB_GRP_CHIP_IDS, // group/chip ID of the memory }; //------------------------------------------------------------------------------ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index 74d35da0..365a9393 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -312,7 +312,7 @@ calc_image_footprint( // (bootloader offset) FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases( i_master_chip_target, - ABS_FBC_GRP_ID_ONLY, + HB_GRP_CHIP_IDS, l_drawer_base_address_nm0, l_drawer_base_address_nm1, l_drawer_base_address_m, @@ -406,7 +406,7 @@ get_bootloader_config_data( // read platform initialized attributes to determine struct content FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_master_chip_target, - EFF_FBC_GRP_CHIP_IDS, + HB_GRP_CHIP_IDS, l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index 3bd71971..dfd5d970 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -227,7 +227,7 @@ p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // = (drawer non-mirrored base address) + (hostboot HRMOR offset) // min MCS base size is 4GB, local HB will always be below FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, - ABS_FBC_GRP_ID_ONLY, + HB_GRP_CHIP_IDS, l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, |
