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* Adding attribute to detect which processor we can use for alt-memoryElizabeth Liner2018-03-072-0/+16
| | | | | | | | | | | | | | | | Change-Id: I5e0435c5828dcaddb8571afdbd298c08400cb0e4 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54585 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54598
* p9_sbe_tracearray -- satsify PRD calls to manage core trace arraysJoe McGill2018-03-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a carryover from prior projects, PRD code currently contains logic which attempts to restart the core trace arrays (via the SBE HWP) after processing a recoverable error emitted from the core. The current HWP flags an error in this case (indicating that the core trace arrays are not SCOM retrievable, which is true for all levels of p9). This generates a customer visible error log with a FW type callout, which is undesirable. This patch is intended to satisfy the current PRD call which intends to reset and start the core traces, without triggering the check mentioned above or attempting to access non-implemented SCOM registers. Ultimately it should have no effect on the actual core tracing, which is managed on p9 by non-SCOM accessible logic in PC. I confirmed with Jim Bishop that the PC logic will not stop tracing on recoverable errors, so there should be no exposure. Change-Id: I77e47f71d18b6a3a762ab52b0f6b42d022153f3b CQ: SW418341 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54857 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54861 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable WOF for Cumulus DD1.0Dan Crowell2018-03-051-0/+7
| | | | | | | | | | | | | | Change-Id: I4d4704098f92004f5a6a141e16b80a2b2dd2a3ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54925 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54932 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable risklevel2, match v44 of security wikiNick Klazynski2018-03-021-3/+3
| | | | | | | | | | | | | | | Change-Id: I9ee4a8c97705ea5aa984c2c0137ed012d50eb658 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54711 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54720 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone support to TP stopclocksSoma BhanuTej2018-03-025-46/+125
| | | | | | | | | | | | | | | | | | Change-Id: I0960ec588156f3df3f863b6c5fa41bbed95e089e RTC: 183048 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53139 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53152 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone MC uses same pll/clock setup as in Cumulus.Ben Gass2018-03-011-1/+16
| | | | | | | | | | | | | | | | | Set HW426891 attribute for Axone. Change-Id: I2c023f3f7cd4060d5acd9bc7ce39bd58b5c56c05 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54069 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54076 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: Support Suspend Entry/Exit and Fix Pig CollisionYue Du2018-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | 1) also cleanup todos in Stop Hcode 2) make STOP3 complete trans in SSH Key_Cronus_Test=PM_REGRESS Change-Id: I28a146e15e455f09f8d8ff588e122d5ecf34110a CQ: SW416550 CQ: HW437955 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54660 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54664 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add support for p9c 1.2Ben Gass2018-02-235-20/+73
| | | | | | | | | | | | | | | | | Also initial mk files for p9n 2.3, but p9c 1.2 will be first. Change-Id: Ia73aba37be5bcf64b1b2cfe5b1ed153b189c7777 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53909 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54542 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add Cumulus DD1.1 initsNick Klazynski2018-02-231-46/+291
| | | | | | | | | | | | | | | | | | | | | | | CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 cmvc-prereq: 1046552 cmvc-prereq: 1045908 Change-Id: I3752f5b5868d7cc8ed3ffdf69a13025989a47eaa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54270 Dev-Ready: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54284 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM_SPWKUP: Clear wakeup notify select bit to enable auto special wakeupGreg Still2018-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | - Deal with Hostboot cores coming out of istep 4 Key_Cronus_Test=PM_REGRESS Change-Id: Ie990d82eed0cb5ab3c71752a557d2f5b197d5642 CQ:SW412666 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54140 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54166 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* LPC: Add empty files for mirroring to HB, PPE, HWSVJoachim Fenkes2018-02-222-0/+50
| | | | | | | | | | Change-Id: If904019d1a847136be3e553302ab5e29ae0a8f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54482 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54508 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Additional risk level support - (step 2) Updating the image w/RL2Claus Michael Olsen2018-02-172-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322
* Updating NCU tlbie pacing dialsLuke C. Murray2018-02-171-4/+4
| | | | | | | | | | | | | | | | | | | This setting improves tlbie latencies that were measured on IBMi. Also commit generated initfile changes causing Jenkins compliation failure. Change-Id: I206fa3c8f07859d44f6f82f3eadebf6f11352637 CQ: HW438757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54157 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54179 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add attribute to give platform more control over PM_RESETChristian Geddes2018-02-161-1/+17
| | | | | | | | | | | | | | | | | | | | | | | The PM_RESET hwp calls special wakeup enable on all EX targets, then will clear auto-special wakeup bit on the core if special wakeup is done. In some cases hostboot does not want these steps of the PM_RESET. This attribute gives the platform the ability to decide if they want to enable special wakeup and clear autowakeup on the cores during PM_RESET CQ:SW412666 Change-Id: I8f2e40f4b122f3ff6a048fa6931a1e47f89d3e4f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53953 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53991 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* hwpErrors: Use wildcard instead of explicit listJoachim Fenkes2018-02-162-88/+2
| | | | | | | | | | | | The makefile was including all XMLs but one (that was unused) anyway. Switch to wildcard so we don't have to explicitly touch hwpErrors.mk every time we add an error XML file. Change-Id: I127dcb75ab3ecb0dadaf73e06d6f6fd3e8294524 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54212 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Protect Firmware from exposure to HW423533Lennard Streat2018-02-151-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iaf1a83505ed9bdd9e79bfc46157856263c392736 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53783 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53802 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add TM WAT workaround; NDD2.2 and CDD1.1 onlyNick Klazynski2018-02-151-0/+24
| | | | | | | | | | | | | | | | Change-Id: I376860a1530ce8ba467d18ea97c0da4e6672e53f CQ: HW436858 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54056 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54073 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disabling WOF and VDM for Nimbus DD2.0Dan Crowell2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Modified the checks to disable WOF by default for Nimbus DD2.0 since most parts have invalid module vpd. Also changed the severity that is used to log errors getting a WOF table to make them visible logs. Without this change we won't know why the lookup failed in many cases. Change-Id: Ic8fd9b4bdc23311897363552f0c88fa2b1b0247b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53274 Reviewed-by: Francesco A. Campisano <campisan@us.ibm.com> Dev-Ready: Francesco A. Campisano <campisan@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53288 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Re-submit Axone updatesBen Gass2018-02-154-35/+266
| | | | | | | | | | | | | | | | | | | | | | | The original patch: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/45266/ was merged prematurely. It was reverted in: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/50703/ pre-commit-actions updated to call code-beautifier twice. Some generated code for initfiles changes between first and second passes. Change-Id: I25bdc2ceaf9636a2f6559775bc8cb9616848c9d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50741 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50961 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FIR + RAS XML updatesJoe McGill2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | p9_sbe_scominit.C mask PBCENT FIR bit 5, rely on action of unit master specific FIR bits to drive attention generation on any cresp address error condition Change-Id: I3c23aeecd426687fe91d37aadfd5ca6243c4a4b3 CQ: SW417475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54067 Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Mask TP LFIR for non PPE mode - p9_sbe_commonSoma BhanuTej2018-02-151-1/+9
| | | | | | | | | | | | | Change-Id: Ib8940710cadc62228be70bf60e98673ece171e10 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54024 Reviewed-by: PRADEEP N. CHATNAHALLI <pradeepcn@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54025
* Extend PM Reset flow to collect PM FFDC to HOMERAmit Tendolkar2018-02-152-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | - extend the base flow to ensure ffdc gets collected to homer - revise error xmls - misc changes to handle pm recovery flow triggered via Malf Alert Key_Cronus_Test=PM_REGRESS Change-Id: I12148ed227efe4613332ae76ff142c1d82855f20 RTC: 153979 CQ: SW416537 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53522 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53532 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable mixed core xlate; Enable xlate protection feature; Disable LSU clockgateNick Klazynski2018-02-131-0/+72
| | | | | | | | | | | | | | | | | Change-Id: I1fbc2c79330520d6033adfafe85a89fc71ed3fb0 CQ: HW437820 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53911 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53917 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enforce strict 512 GB per socket limit on Witherspoon memory map (part2)Joe McGill2018-02-122-3/+6
| | | | | | | | | | | | | | | | | | | | | | | first commit merged before HW testing was complete, and caused issue with skiboot's detection of the MCD workaround mechanism this update restores the chip address extension HW programming to 0x7, (to avoid a coreq skiboot change) but should still restrict the allocation to lie within the first 512 GB of address space on each socket Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53642 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enforce strict 512 GB per socket limit on Witherspoon memory mapJoe McGill2018-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SW415901 exposed a problem with the current implementation of extended addressing for Witherspoon Coral systems. With fully configured memory present in the system (8x64GB=512GB per socket), GARDing a DIMM will currently result in: - group of 6 fullying occupying 0-512GB address space - group of 1 mapped at 8TB region (2nd extended addressing region) The single group mapping has RA bit 20 active, which is problematic for the NVIDIA device driver. p9_fbc_utils.H p9.trace.scan.initfile for HW423589 option 2, enable chip address extension for chip ID LSB RA bit 21 only. This creates only one 4TB extended addressing region per socket. indirectly, this limits DIMMs to map into the 512 GB region with RA bit 21=0 and should cause an IPL failure if more than 512 GB is plugged or the memory grouping algorithm attempts to spill beyond 512 GB on a given chip p9_mss_eff_grouping.C prohibit formation of group sizes 6 and 3 when HW423589 option2 WA is active Change-Id: I997c080a2821cf3c556a4f8b35d5e0fdb34da500 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53411 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.npu.scom.initfile -- limit DCP0 credits for HW437173Joe McGill2018-02-111-0/+18
| | | | | | | | | | | | | | | | Change-Id: Id1dca730debe012d706fb9eb2fa236c7fb92fab8 CQ: HW437173 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53649 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RYAN BLACK <rblack@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53671 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating HW414700 to also apply to Cumulus DD10Jenny Huynh2018-02-111-2/+9
| | | | | | | | | | | | | | | | | Change-Id: I565fe99adc16d8b2c56d6ca8365c77ae5bad0aef CQ: HW414700 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50287 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50369 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock""Sachin Gupta2018-02-102-5/+97
| | | | | | | | | | | | | | | | This reverts commit 59635779caa45afd1be7e483d232bb317b6c0989. Change-Id: I93708f97e5a5c44e9af1957230bb68a754e98ebb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52838 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53499 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* CME Code Size Reduction ATTEMPT#3Michael Floyd2018-02-074-20/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -- some IOTA kernel cleanup -- also add checking for IOTA execution stack overflow -- re-coded to eliminate some math library macro usage -- added native 16-bit multiply -- re-coded to remove redundancy from external interrupt handler -- removed dec handler (optional define) and other minor cleanup -- fixed Interrupt initialization code in std_init (all PPE images) -- always inline pstate_db0_clip_bcast & update_vdm_jump_values_in_dpll -- optimized pls calculation code -- optimized pstate init, db1 handler, core good handling -- optimized pmcr requests and pmsr updates (always write for both cores) Key_Cronus_Test=PM_REGRESS Change-Id: If48fec5832bd5e46cb89f0d6a97d90a488e8ff7b CQ: SW415503 RTC: 178789 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53381 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53385 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* cresp address error handling updatesJoe McGill2018-02-011-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit sets up the FBC trace arrays to stop on a combined response address error, for MPIPL FFDC collection. It also adjusts the FIR configuration for several units, to trigger a system checkstop (based on their own LFIR) if they master a command which recieves a combined response address error cresp, and we do not support MPIPL from that condition. Unlike in past projects, the FBC level cresp address error FIR bit cannot be set to checkstop (in order to support MPIPL scenarios where the unacknowledged access eminates from the core) FIR action bits modified: PSIHB bits 15:20 PBA bit 1 Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f CQ: SW411054 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52634 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Two LTPTR workarounds, remove LTPTR serialization, Fix TB IMCNick Klazynski2018-02-011-18/+32
| | | | | | | | | | | | | | | | | Change-Id: I8a87781a9b78eef0a504d6c1eb2dfdfeb53e7ff7 CQ: HW435226 CQ: HW435395 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52929 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52954 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_build_smp -- use ADU chipops to switch fabric configuration part #2Joe McGill2018-01-301-1/+4
| | | | | | | | | | | | | | | | | | | | p9_build_smp HWP code is modified to invoke new p9_putmemproc FAPI HWP via FAPI_CALL_SUBROUTINE HB platform must invoke SBE chipop under the covers for security Cronus may directly invoke p9_putmemproc body in an insecure system Change-Id: I34b90ce906e8caaf3ce86e728228f634ce136d33 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49692 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49694 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* shift XBUS FIR programming inits for secure bootJoe McGill2018-01-261-1/+127
| | | | | | | | | | | | | | | | | | | | | | general approach: - enable runtime FIR settings in SBE code, for all present XBUS regions - remove FIR initialization from HB code which runs prior to SMP build - update HB HWPs to re-mask XBUSes which are present but not functionally used CQ: SW409902 CQ: SW409903 CQ: SW409905 Change-Id: I378ed2ca39c0d5be894420bfc3257e41e3e95de5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50519 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50528 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Remove workaround for DD1 SW reset for XIVESachin Gupta2018-01-264-292/+22
| | | | | | | | | | | | | | | | Change-Id: Ic2cf3510350aa00c0641cc910824000bf58d8276 RTC: 177741 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52512 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52515 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Make SBE errors recoverable - p9_sbe_commonSoma BhanuTej2018-01-261-3/+3
| | | | | | | | | | | | | | | | Change-Id: I145734f290153eb6f7bc9810917026260d490260 CQ: SW413535 Backport: release-fips910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52513 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52521
* p9_xbus_fir_utils.H -- create header for definition of XBUS related FIR settingsJoe McGill2018-01-251-0/+97
| | | | | | | | | | | | independent commit to create pre-req for 50519 Change-Id: I69a4c497c2def46f396d1c37594b26c9bea263d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52390 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52580 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HDCT: Remove core trace arrays, permanent P9 erratumJoachim Fenkes2018-01-251-3/+4
| | | | | | | | | | | | | | | | | CQ: SW414265 Change-Id: I1518e78d87e1a9a115cec26cda75c3708ae4c421 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52350 Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52352 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Implement security IMCs, based on v29 of wikiNick Klazynski2018-01-231-6/+149
| | | | | | | | | | | | | | | | | | /wiki/W9f19463eb4a5_44ca_ad0c_a35ccf4e7d1e/page/IMCs%20by%20Project Change-Id: Ib6b7ec4daf84bf9125bc68a4a4f287175a385b07 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52206 Dev-Ready: James N Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52214 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* P9 SBE EOL Toggle SBE ProcedureChris Steffen2018-01-232-0/+153
| | | | | | | | | | | Change-Id: I3ccf9c6f24e9f5f4c1af83f6fbc44f7ca080c2cc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48693 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gary A. Peterson <garyp@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52414
* STOP: Fix PLS deepest when stop4+ due to self restore wakeupYue Du2018-01-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I4cc1e50a848d627f0ec3917bb8ebd39f20dc9466 CQ: HW420338 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51719 Reviewed-by: YUE DU <daviddu@us.ibm.com> Dev-Ready: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52219 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: VDM Prolonged Droop FixRahul Batra2018-01-191-1/+16
| | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I73d38d6029a5b84590d1081855e12c145a535869 CQ: SW413192 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51338 Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51345 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add new TM IMC, Add TLBIE hangbusterNick Klazynski2018-01-191-0/+24
| | | | | | | | | | | | | | | Change-Id: Ief523bd33a34a6a96f61664f6ab3545d9dc15d98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52050 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52121 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Register FFDC call is handled within machine_check_handlerRaja Das2018-01-191-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Within the PK interrupt vector, if you have a function call from one function to another, it needs branch link instruction, but since the BL is already being used to jump from software context to the PK Vectored Interrupt context, the function call from within will corrupt the Link register. For interrupts like data_storage, instruction_storage, alignment_exception and program_exception, the save-off will capture the LR registers to indicate which interrupt was getting executed when halt happened. For Machine check handler, LR won't be valid. Change-Id: Iee17b37acd438c7bee2c956cac2de3ce64d04441 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51587 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51588
* Fix three NDD2.1 dials and add new NDD2.2 workaroundsNick Klazynski2018-01-171-14/+189
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I0d0aebc925c963a32e2cf2266e833df84a799235 CQ: HW409194 CQ: HW407065 CQ: HW419541 CQ: HW430944 CQ: HW417829 CQ: HW422533 CQ: HW414249 CQ: HW432749 CQ: HW414146 CQ: HW433125 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51677 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51685 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Zepplin:Remove dd level check for cumulus under PPB codePrasad Bg Ranganath2018-01-141-7/+0
| | | | | | | | | | | | | | | Change-Id: I5435bef91381ade76a1439a842fa90b86e17aab3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51599 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51604 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add FABRIC_PRESENT_GROUPS system attributeChristian Geddes2018-01-141-1/+17
| | | | | | | | | | | | | | | | | | Bit mask of group IDs which will be present in the fully configured CEC configuration. Change-Id: I43b06e856d2b285bb919025926b914d3ec4de451 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51692 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51701 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Ignore allow_reg_wakeup in cache contained modeBrian Vanderpool2018-01-141-0/+28
| | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: If2916c99b37c4ce56ad1cf6f6957d67497fac5ab CQ: SW412668 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51394 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Dev-Ready: Brian T. Vanderpool <vanderp@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51471 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Workaround for Quaint Gate, Angry ReindeerJenny Huynh2018-01-141-4/+29
| | | | | | | | | | | | | | | | | Change-Id: Iee18d460dc99de59eb0b1f8891dad1e8698e3208 CQ:HW430944 CQ:HW432070 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51370 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51428 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* jgr171017 Setting changes for Obus boardwire vs cableJohn Rell2018-01-141-0/+24
| | | | | | | | | | | | | | | | Change-Id: I6c64841173f036c4898c199ef1615046a3974dcc CQ: HW422471 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48525 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50964 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Large update for securityNick Klazynski2018-01-141-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | - IMC6 changed to implement special nop - IMC7 serializes bcctr for NDD2.2/CDD1.1 - mttrig2 moved to mttrig0 - mttrig2 now causes an L1 flush on NDD2.2/CDD1.1 - Force private L1D - branch hint bits always honored - enable new TM mode for NDD2.2 Change-Id: I3b724f6d742b9ba321ea1abbfa6bbc7d5482b8ed CQ: HW430733 CQ: SW410726 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50872 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51025 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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