| Commit message (Expand) | Author | Age | Files | Lines |
* | p9_sbe_tp_switch_gears, p9_sbe_gear_switcher: Level 3 | Joachim Fenkes | 2017-06-01 | 4 | -9/+14 |
* | P9 Cumulus InitCompiler supportis - Part 3 | Thi Tran | 2017-06-01 | 3 | -11/+20 |
* | p9_sbe_common: Level 3 | Joachim Fenkes | 2017-06-01 | 2 | -21/+48 |
* | update owner comments in ADU, PBA, TOD HWPs | Joe McGill | 2017-06-01 | 16 | -19/+17 |
* | Stopclocks procedure to stop PLL region also | Soma BhanuTej | 2017-05-31 | 2 | -9/+8 |
* | future proof EC feature attributes, add missing P9N DD2 inits | Joe McGill | 2017-05-31 | 2 | -19/+19 |
* | Check scrach register 3 bit 6 before potentially disabling security | Nick Bofferding | 2017-05-29 | 1 | -6/+16 |
* | L3 update -- p9_sbe_fabricinit | Joe McGill | 2017-05-28 | 2 | -16/+11 |
* | L3 updates -- p9_build_smp, p9_fbc_utils | Joe McGill | 2017-05-28 | 2 | -33/+38 |
* | p9_perv_sbe_cmn: Level 3 | Joachim Fenkes | 2017-05-27 | 2 | -4/+4 |
* | support chip swap in memory map via FBC XOR mask programming | Joe McGill | 2017-05-27 | 8 | -86/+167 |
* | p9_sbe_mcs_setup/p9_revert_sbe_mcs_setup -- add support for Cumulus | Peng Fei GOU | 2017-05-25 | 1 | -2/+69 |
* | L3 update -- p9_sbe_scominit | Joe McGill | 2017-05-25 | 2 | -24/+39 |
* | Fixing p9_pba_access.C to return FFDC for error from PBA status check | Thi Tran | 2017-05-21 | 1 | -5/+9 |
* | Level 3 : OCB & OCC procedures | Sangeetha T S | 2017-05-19 | 4 | -22/+48 |
* | p9_sbe_nest_initf -- add HWP support to scan n3_br_fure | Joe McGill | 2017-05-19 | 1 | -0/+11 |
* | moving thread_mode to scan init, new dd2 dial is scanonly | Emmanuel Sacristan | 2017-05-12 | 1 | -125/+3 |
* | Pstate: Remove legacy VDM code | Christopher M. Riedl | 2017-05-12 | 4 | -25/+8 |
* | p9_hcd_cache_dcc_skewadjust_setup | Anusha Reddy Rangareddygari | 2017-05-11 | 1 | -16/+141 |
* | NMMU Nimbus dd2 scom/scan updates, updated comments | Emmanuel Sacristan | 2017-05-11 | 1 | -37/+222 |
* | Setting up nmmu lco targets/min based on valid exs | Jenny Huynh | 2017-05-11 | 1 | -1/+51 |
* | ADU Level 3 code, changed owner to Josh, and added comments | CHRISTINA L. GRAVES | 2017-05-11 | 7 | -213/+251 |
* | PBA Level 3 code, changed owner to Josh, and added comments | CHRISTINA L. GRAVES | 2017-05-11 | 7 | -129/+150 |
* | p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34s | Joachim Fenkes | 2017-05-04 | 2 | -4/+2 |
* | L3 initfile updates | Alex Taft | 2017-04-28 | 1 | -6/+0 |
* | changed hang to recoverable form checkstop | Emmanuel Sacristan | 2017-04-28 | 1 | -2/+2 |
* | p9_sbe_set_lqa and p9_sbe_hb_structures changed owner to Josh | CHRISTINA L. GRAVES | 2017-04-28 | 1 | -2/+2 |
* | Initf proc updates | Anusha Reddy Rangareddygari | 2017-04-28 | 4 | -161/+471 |
* | Add NCU/L3 dials for HW396230 to p9.ncu.scom.initfile | CHRISTINA L. GRAVES | 2017-04-28 | 4 | -5/+54 |
* | IPL: Add global checkstop FIR check in Istep4 | Yue Du | 2017-04-28 | 2 | -22/+62 |
* | using literal definitions | Soma BhanuTej | 2017-04-19 | 2 | -61/+57 |
* | p9_sbe_startclock_chiplets updates | Anusha Reddy Rangareddygari | 2017-04-19 | 1 | -0/+21 |
* | p9_htm_setup -- cleanup start behavior for multi-chip systems | Joe McGill | 2017-04-13 | 1 | -8/+10 |
* | Need to disable fast path and cmd bypass for HB load | Dean Sanner | 2017-04-11 | 1 | -1/+12 |
* | Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabled | CHRISTINA L. GRAVES | 2017-04-06 | 1 | -0/+4 |
* | Adding epsilon divider variable to cache initfiles | Luke Murray | 2017-04-06 | 2 | -12/+24 |
* | Updating cache epsilon initfile equation | Luke Murray | 2017-04-06 | 2 | -94/+14 |
* | Added suspend_io in p9_sbe_check_quiesce procedure | Raja Das | 2017-04-06 | 1 | -0/+3 |
* | Build p9n 10 and 20 by default. | Ben Gass | 2017-04-06 | 1 | -10/+50 |
* | Do the real LPC reset for DD2 | CHRISTINA L. GRAVES | 2017-04-06 | 2 | -1/+33 |
* | literal definitions | Anusha Reddy Rangareddygari | 2017-04-06 | 4 | -62/+65 |
* | Add workaround so p9_suspend_io can be called systems with no PHB5 | crgeddes | 2017-03-31 | 1 | -0/+22 |
* | HW404292: Assert analog fence in cache_chiplet_reset | Yue Du | 2017-03-31 | 3 | -2/+10 |
* | HW405243/IPL: Assert/drop pcb_mux_disable around quad power off | Yue Du | 2017-03-31 | 3 | -6/+61 |
* | update DPLL and IVRM inits | Joe McGill | 2017-03-31 | 2 | -4/+5 |
* | IPL: Change select_ex to use core/eq targets instead of perv | Yue Du | 2017-03-31 | 1 | -25/+23 |
* | support customization of Nimbus DD1 PCI reference clock speed | Joe McGill | 2017-03-31 | 2 | -0/+38 |
* | p9_sbe_chiplet_reset,p9_sbe_arrayinit | Anusha Reddy Rangareddygari | 2017-03-29 | 2 | -4/+65 |
* | Enablement of additional eq_ana_bndy rings for Nimbus DD2 | Sumit Kumar | 2017-03-24 | 1 | -3/+3 |
* | Include p9_ring_id.h or p9_ringId.H | Kahn Evans | 2017-03-23 | 1 | -0/+1 |