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path: root/src/import/chips/p9/procedures/hwp
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* p9_sbe_tp_switch_gears, p9_sbe_gear_switcher: Level 3Joachim Fenkes2017-06-014-9/+14
* P9 Cumulus InitCompiler supportis - Part 3Thi Tran2017-06-013-11/+20
* p9_sbe_common: Level 3Joachim Fenkes2017-06-012-21/+48
* update owner comments in ADU, PBA, TOD HWPsJoe McGill2017-06-0116-19/+17
* Stopclocks procedure to stop PLL region alsoSoma BhanuTej2017-05-312-9/+8
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-05-312-19/+19
* Check scrach register 3 bit 6 before potentially disabling securityNick Bofferding2017-05-291-6/+16
* L3 update -- p9_sbe_fabricinitJoe McGill2017-05-282-16/+11
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2017-05-282-33/+38
* p9_perv_sbe_cmn: Level 3Joachim Fenkes2017-05-272-4/+4
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-278-86/+167
* p9_sbe_mcs_setup/p9_revert_sbe_mcs_setup -- add support for CumulusPeng Fei GOU2017-05-251-2/+69
* L3 update -- p9_sbe_scominitJoe McGill2017-05-252-24/+39
* Fixing p9_pba_access.C to return FFDC for error from PBA status checkThi Tran2017-05-211-5/+9
* Level 3 : OCB & OCC proceduresSangeetha T S2017-05-194-22/+48
* p9_sbe_nest_initf -- add HWP support to scan n3_br_fureJoe McGill2017-05-191-0/+11
* moving thread_mode to scan init, new dd2 dial is scanonlyEmmanuel Sacristan2017-05-121-125/+3
* Pstate: Remove legacy VDM codeChristopher M. Riedl2017-05-124-25/+8
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-111-16/+141
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-05-111-37/+222
* Setting up nmmu lco targets/min based on valid exsJenny Huynh2017-05-111-1/+51
* ADU Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-117-213/+251
* PBA Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-117-129/+150
* p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34sJoachim Fenkes2017-05-042-4/+2
* L3 initfile updatesAlex Taft2017-04-281-6/+0
* changed hang to recoverable form checkstopEmmanuel Sacristan2017-04-281-2/+2
* p9_sbe_set_lqa and p9_sbe_hb_structures changed owner to JoshCHRISTINA L. GRAVES2017-04-281-2/+2
* Initf proc updatesAnusha Reddy Rangareddygari2017-04-284-161/+471
* Add NCU/L3 dials for HW396230 to p9.ncu.scom.initfileCHRISTINA L. GRAVES2017-04-284-5/+54
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-282-22/+62
* using literal definitionsSoma BhanuTej2017-04-192-61/+57
* p9_sbe_startclock_chiplets updatesAnusha Reddy Rangareddygari2017-04-191-0/+21
* p9_htm_setup -- cleanup start behavior for multi-chip systemsJoe McGill2017-04-131-8/+10
* Need to disable fast path and cmd bypass for HB loadDean Sanner2017-04-111-1/+12
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-04-061-0/+4
* Adding epsilon divider variable to cache initfilesLuke Murray2017-04-062-12/+24
* Updating cache epsilon initfile equationLuke Murray2017-04-062-94/+14
* Added suspend_io in p9_sbe_check_quiesce procedureRaja Das2017-04-061-0/+3
* Build p9n 10 and 20 by default.Ben Gass2017-04-061-10/+50
* Do the real LPC reset for DD2CHRISTINA L. GRAVES2017-04-062-1/+33
* literal definitionsAnusha Reddy Rangareddygari2017-04-064-62/+65
* Add workaround so p9_suspend_io can be called systems with no PHB5crgeddes2017-03-311-0/+22
* HW404292: Assert analog fence in cache_chiplet_resetYue Du2017-03-313-2/+10
* HW405243/IPL: Assert/drop pcb_mux_disable around quad power offYue Du2017-03-313-6/+61
* update DPLL and IVRM initsJoe McGill2017-03-312-4/+5
* IPL: Change select_ex to use core/eq targets instead of pervYue Du2017-03-311-25/+23
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-312-0/+38
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-292-4/+65
* Enablement of additional eq_ana_bndy rings for Nimbus DD2Sumit Kumar2017-03-241-3/+3
* Include p9_ring_id.h or p9_ringId.HKahn Evans2017-03-231-0/+1
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