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| author | Jenny Huynh <jhuynh@us.ibm.com> | 2017-05-03 17:56:24 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-11 10:12:24 -0400 |
| commit | 7d841a3bbbd986f5d07654e3b20e7c5a8fbea290 (patch) | |
| tree | 995b63de978b2a2cf35da9fbac5ab7d1e76bdf5f /src/import/chips/p9/procedures/hwp | |
| parent | b36bfb2e0f77258355cf2a398d5ef2f9e1a9aff9 (diff) | |
| download | talos-sbe-7d841a3bbbd986f5d07654e3b20e7c5a8fbea290.tar.gz talos-sbe-7d841a3bbbd986f5d07654e3b20e7c5a8fbea290.zip | |
Setting up nmmu lco targets/min based on valid exs
Change-Id: I9e1a0aadae5a43f4ddaab2969cd48900585978b3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40051
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40080
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 52 |
1 files changed, 51 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index da0bd061..84aeca3c 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -47,6 +47,7 @@ #include <p9_mmu_scom.H> #include <p9_misc_scom_addresses.H> +#include <p9_misc_scom_addresses_fld.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> #include <p9_xbus_scom_addresses.H> @@ -450,8 +451,12 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // execute NMMU initfile { - FAPI_DBG("Executing NMMU initfile"); fapi2::ReturnCode l_rc; + fapi2::buffer<uint64_t> l_scom_data; + auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>(); + uint8_t l_lco_min; + + FAPI_DBG("Executing NMMU initfile"); FAPI_EXEC_HWP(l_rc, p9_mmu_scom, i_target, FAPI_SYSTEM); if (l_rc) @@ -460,6 +465,51 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) fapi2::current_err = l_rc; goto fapi_try_exit; } + + // setup NMMU lco config (for all chips, but lco is only enabled for ndd2+) + // > NMMU.MM_FBC.CQ_WRAP.NXCQ_SCOM.LCO_TARG_CONFIG + // enable only valid EXs + // > NMMU.MM_FBC.CQ_WRAP.NXCQ_SCOM.LCO_TARG_MIN + // if there are more than 8 EXs, set to 8 + // if 8 EXs or less, set to one less than number of EXs + // if 0 EXs or 1 EX, set to zero/one respectively + FAPI_TRY(fapi2::getScom(i_target, PU_NMMU_MMCQ_PB_MODE_REG, l_scom_data), + "Error from getScom (PU_NMMU_MMCQ_PB_MODE_REG)"); + + for (auto& l_ex : l_ex_targets) + { + uint8_t l_exid = l_ex.get(); + FAPI_TRY(l_scom_data.setBit(PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG + l_exid), + "Error from setBit (l_scom_data, PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG + l_exid)"); + } + + switch (l_ex_targets.size()) + { + case 0: + l_lco_min = 0; + break; + + case 1: + l_lco_min = 1; + break; + + case 9: + case 10: + case 11: + case 12: + l_lco_min = 8; + break; + + default: + l_lco_min = l_ex_targets.size() - 1; + break; + } + + l_scom_data.insertFromRight<PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN, PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN> + (l_lco_min); + + FAPI_TRY(fapi2::putScom(i_target, PU_NMMU_MMCQ_PB_MODE_REG, l_scom_data), + "Error from putScom (PU_NMMU_MMCQ_PB_MODE_REG)"); } { |
